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[Commit-gnuradio] r5767 - in gnuradio/branches/developers/thottelt: inba
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From: |
thottelt |
|
Subject: |
[Commit-gnuradio] r5767 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib inband/usrp/fpga/megacells simulations |
|
Date: |
Mon, 11 Jun 2007 17:38:59 -0600 (MDT) |
Author: thottelt
Date: 2007-06-11 17:38:59 -0600 (Mon, 11 Jun 2007)
New Revision: 5767
Added:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_2k_1clk.v
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.bsf
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.cmp
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.inc
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k_bb.v
gnuradio/branches/developers/thottelt/simulations/tx.mpf
Log:
started to work on the rx side
Added:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
(rev 0)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2007-06-11 23:38:59 UTC (rev 5767)
@@ -0,0 +1,104 @@
+//`include "../../firmware/include/fpga_regs_common.v"
+//`include "../../firmware/include/fpga_regs_standard.v"
+
+module rx_buffer
+ ( input usbclk,
+ input bus_reset,
+ input reset, // DSP side reset (used here), do not reset registers
+ input reset_regs, //Only reset registers
+ output [15:0] usbdata,
+ input RD,
+ output wire have_pkt_rdy,
+ output reg rx_overrun,
+ input wire [3:0] channels,
+ input wire [15:0] ch_0,
+ input wire [15:0] ch_1,
+ input wire [15:0] ch_2,
+ input wire [15:0] ch_3,
+ input wire [15:0] ch_4,
+ input wire [15:0] ch_5,
+ input wire [15:0] ch_6,
+ input wire [15:0] ch_7,
+ input rxclk,
+ input rxstrobe,
+ input clear_status,
+ input [6:0] serial_addr,
+ input [31:0] serial_data,
+ input serial_strobe,
+ output [15:0] debugbus
+ );
+
+ parameter NUM_CHAN = 2;
+ genvar i ;
+
+ // FX2 Bug Fix
+ reg [8:0] read_count;
+ always @(negedge usbclk)
+ if(bus_reset)
+ read_count <= #1 9'd0;
+ else if(RD & ~read_count[8])
+ read_count <= #1 read_count + 9'd1;
+ else
+ read_count <= #1 RD ? read_count : 9'b0;
+
+ // USB side fifo
+ wire [9:0] rdusedw;
+ wire [9:0] wrusedw;
+ wire [15:0] fifodata;
+ wire WR;
+ wire have_space;
+
+ fifo_1k rx_usb_fifo (
+ .aclr ( reset ),
+ .data ( fifodata ),
+ .rdclk ( ~usbclk ),
+ .rdreq ( RD & ~read_count[8] ),
+ .wrclk ( rxclk ),
+ .wrreq ( WR ),
+ .q ( usbdata ),
+ .rdempty ( ),
+ .rdusedw ( rdusedw ),
+ .wrfull ( ),
+ .wrusedw ( wrusedw ) );
+
+ assign have_pkt_ready = (rdusedw >= 256);
+ assign have_space = (wrusedw < 256);
+
+ // Rx side fifos
+ wire [NUM_CHAN:0] chan_rdreq;
+ wire [15:0] chan_fifodata;
+ wire [NUM_CHAN:0] chan_empty;
+ wire [NUM_CHAN:0] rd_select;
+
+ packet_builer rx_pkt_builer (
+ .rxclk ( rxclk ),
+ .reset ( reset ),
+
+ .chan_rdreq ( chan_rdreq ),
+ .chan_fifodata ( chan_fifodata ),
+ .chan_empty ( chan_empty ),
+
+ .rd_select(rd_select),
+ .WR ( WR ),
+ .fifodata ( fifodata ) );
+
+ generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
+ begin : generate_channel_fifos
+ wire [15:0] data;
+ assign chan_fifodata = (rd_select[i] ? data : 16'bZ);
+
+ fifo_2k_1clk rx_chan_fifo (
+ .aclr ( reset ),
+ .clock ( rxclk ),
+ .data ( data ),
+ .rdreq ( chan_rdreq[i] ),
+ .wrreq ( ),
+ .empty ( chan_empty[i] ),
+ .full ( ),
+ .q ( ),
+ .usedw ( ) );
+ end
+ endgenerate
+
+ assign debugbus = 0;
+endmodule
Property changes on:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
___________________________________________________________________
Name: svn:executable
+ *
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
2007-06-11 21:43:15 UTC (rev 5766)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
2007-06-11 23:38:59 UTC (rev 5767)
@@ -1,127 +1,24 @@
-module usb_fifo_reader (tx_clock, fifodata, pkt_waiting, reset,
- rdreq, done_chan, WR_chan, tx_data_bus, have_space_chan);
+module usb_fifo_reader (
+ input usbclk,
+ input bus_reset,
+ input RD,
+ output rdreq,
+ );
- /* Module parameters */
- parameter NUM_CHAN = 2 ;
- parameter WIDTH = 32 ;
- parameter PKT_SIZE = 512 ;
+ // FX2 Bug Fix
+ reg [8:0] read_count;
+ always @(negedge usbclk)
+ if(bus_reset)
+ read_count <= #1 9'd0;
+ else if(RD & ~read_count[8])
+ read_count <= #1 read_count + 9'd1;
+ else
+ read_count <= #1 RD ? read_count : 9'b0;
+
+ assign rdreq = RD & ~read_count[8];
- input wire tx_clock ;
- input wire reset ;
- input wire [WIDTH-1:0] fifodata ;
- input wire pkt_waiting ;
- input wire [NUM_CHAN:0] have_space_chan ;
- output reg rdreq ;
- output reg [NUM_CHAN:0] done_chan ;
- output reg [NUM_CHAN:0] WR_chan ;
- output reg [WIDTH-1:0] tx_data_bus ;
-
-
-
- /* States definition */
- `define IDLE 3'd0
- `define WAIT 3'd1
- `define READ_HEADER 3'd2
- `define FORWARD_DATA 3'd3
- `define SKIP_REST 3'd4
-
- /* Channel Ids */
- `define TXCHAN0 5'h0
- `define TXCHAN1 5'h1
- `define TXCMD 5'h1F
-
- /* Local registers */
- reg [2:0] reader_state ;
- reg [4:0] channel ;
- reg [9:0] pkt_length ;
- reg [9:0] read_length ;
- /* State Machine */
- always @(posedge tx_clock)
- begin
- if (reset)
- begin
- reader_state <= `IDLE ;
- rdreq <= 0 ;
- WR_chan <= {(NUM_CHAN+1){1'b0}} ;
- done_chan <= {(NUM_CHAN+1){1'b0}} ;
- end
- else
- begin
-
- case(reader_state)
- `IDLE:
- begin
- reader_state <= pkt_waiting ? `WAIT : `IDLE
;
- done_chan <= {(NUM_CHAN+1){1'b0}} ;
- rdreq <= pkt_waiting ;
- end
-
- /* Wait for the fifo's data to show up */
- `WAIT:
- begin
- reader_state <= `READ_HEADER ;
- rdreq <= 0 ;
- end
-
- `READ_HEADER:
- begin
- /* Read header fields */
- channel <= (fifodata[20:16]) ;
- pkt_length <= fifodata[8:0] + 10'd8 ;
- read_length <= 10'd0 ;
-
- if (have_space_chan[channel])
- begin
- reader_state <= `FORWARD_DATA ;
- rdreq <= 1;
- end
- end
-
- `FORWARD_DATA:
- begin
- read_length <= read_length + 10'd4 ;
-
- // If end of payload...
- if (read_length == pkt_length)
- begin
- reader_state <= rdreq ? `SKIP_REST : `IDLE ;
-
- /* Data pushing done */
- WR_chan <= {(NUM_CHAN+1){1'b0}} ;
-
- /* Notify next block */
- done_chan[channel] <= 1 ;
-
- end
- else
- WR_chan[channel] <= 1 ;
-
- if (read_length == PKT_SIZE - 8)
- rdreq <= 0;
-
- /* Forward data */
- tx_data_bus <= fifodata ;
- end
-
- `SKIP_REST:
- begin
- read_length <= read_length + 10'd4;
- done_chan <= {(NUM_CHAN+1){1'b0}} ;
-
- if (read_length == PKT_SIZE - 4)
- reader_state <= `IDLE ;
- else if (read_length == PKT_SIZE - 8)
- rdreq <= 0 ;
- end
-
- default:
- begin
- reader_state <= `IDLE;
- end
- endcase
- end
- end
+
endmodule
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
2007-06-11 21:43:15 UTC (rev 5766)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
2007-06-11 23:38:59 UTC (rev 5767)
@@ -3,7 +3,7 @@
#(parameter BUS_WIDTH = 16,
parameter NUM_CHAN = 2,
parameter FIFO_WIDTH = 32)
- (//FX2 Side
+ ( //FX2 Side
input bus_reset,
input usbclk,
input WR_fx2,
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.bsf
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.bsf
2007-06-11 21:43:15 UTC (rev 5766)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.bsf
2007-06-11 23:38:59 UTC (rev 5767)
@@ -26,8 +26,8 @@
(port
(pt 0 32)
(input)
- (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size
8)))
- (text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size
8)))
+ (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size
8)))
+ (text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size
8)))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
@@ -75,15 +75,15 @@
(port
(pt 160 72)
(output)
- (text "wrusedw[7..0]" (rect 0 0 84 14)(font "Arial" (font_size
8)))
- (text "wrusedw[7..0]" (rect 69 66 132 79)(font "Arial"
(font_size 8)))
+ (text "wrusedw[8..0]" (rect 0 0 84 14)(font "Arial" (font_size
8)))
+ (text "wrusedw[8..0]" (rect 69 66 132 79)(font "Arial"
(font_size 8)))
(line (pt 160 72)(pt 144 72)(line_width 3))
)
(port
(pt 160 96)
(output)
- (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
- (text "q[31..0]" (rect 105 90 141 103)(font "Arial" (font_size
8)))
+ (text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+ (text "q[15..0]" (rect 105 90 141 103)(font "Arial" (font_size
8)))
(line (pt 160 96)(pt 144 96)(line_width 3))
)
(port
@@ -96,12 +96,12 @@
(port
(pt 160 136)
(output)
- (text "rdusedw[7..0]" (rect 0 0 80 14)(font "Arial" (font_size
8)))
- (text "rdusedw[7..0]" (rect 73 130 135 143)(font "Arial"
(font_size 8)))
+ (text "rdusedw[8..0]" (rect 0 0 80 14)(font "Arial" (font_size
8)))
+ (text "rdusedw[8..0]" (rect 73 130 135 143)(font "Arial"
(font_size 8)))
(line (pt 160 136)(pt 144 136)(line_width 3))
)
(drawing
- (text "32 bits x 256 words" (rect 63 156 144 168)(font "Arial"
))
+ (text "16 bits x 512 words" (rect 63 156 144 168)(font "Arial"
))
(line (pt 16 16)(pt 144 16)(line_width 1))
(line (pt 144 16)(pt 144 168)(line_width 1))
(line (pt 144 168)(pt 16 168)(line_width 1))
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.cmp
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.cmp
2007-06-11 21:43:15 UTC (rev 5766)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.cmp
2007-06-11 23:38:59 UTC (rev 5767)
@@ -17,15 +17,15 @@
PORT
(
aclr : IN STD_LOGIC := '0';
- data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
- rdusedw : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ rdusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
wrfull : OUT STD_LOGIC ;
- wrusedw : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+ wrusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
end component;
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.inc
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.inc
2007-06-11 21:43:15 UTC (rev 5766)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.inc
2007-06-11 23:38:59 UTC (rev 5767)
@@ -16,7 +16,7 @@
FUNCTION fifo_1k
(
aclr,
- data[31..0],
+ data[15..0],
rdclk,
rdreq,
wrclk,
@@ -24,9 +24,9 @@
)
RETURNS (
- q[31..0],
+ q[15..0],
rdempty,
- rdusedw[7..0],
+ rdusedw[8..0],
wrfull,
- wrusedw[7..0]
+ wrusedw[8..0]
);
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.v
===================================================================
--- gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.v
2007-06-11 21:43:15 UTC (rev 5766)
+++ gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.v
2007-06-11 23:38:59 UTC (rev 5767)
@@ -47,27 +47,27 @@
wrusedw);
input aclr;
- input [31:0] data;
+ input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
- output [31:0] q;
+ output [15:0] q;
output rdempty;
- output [7:0] rdusedw;
+ output [8:0] rdusedw;
output wrfull;
- output [7:0] wrusedw;
+ output [8:0] wrusedw;
wire sub_wire0;
- wire [7:0] sub_wire1;
+ wire [8:0] sub_wire1;
wire sub_wire2;
- wire [31:0] sub_wire3;
- wire [7:0] sub_wire4;
+ wire [15:0] sub_wire3;
+ wire [8:0] sub_wire4;
wire rdempty = sub_wire0;
- wire [7:0] wrusedw = sub_wire1[7:0];
+ wire [8:0] wrusedw = sub_wire1[8:0];
wire wrfull = sub_wire2;
- wire [31:0] q = sub_wire3[31:0];
- wire [7:0] rdusedw = sub_wire4[7:0];
+ wire [15:0] q = sub_wire3[15:0];
+ wire [8:0] rdusedw = sub_wire4[8:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
@@ -92,11 +92,11 @@
dcfifo_component.clocks_are_synchronized = "FALSE",
dcfifo_component.intended_device_family = "Cyclone",
dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
- dcfifo_component.lpm_numwords = 256,
+ dcfifo_component.lpm_numwords = 512,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
- dcfifo_component.lpm_width = 32,
- dcfifo_component.lpm_widthu = 8,
+ dcfifo_component.lpm_width = 16,
+ dcfifo_component.lpm_widthu = 9,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON";
@@ -113,7 +113,7 @@
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
-// Retrieval info: PRIVATE: Depth NUMERIC "256"
+// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
@@ -125,7 +125,7 @@
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
-// Retrieval info: PRIVATE: Width NUMERIC "32"
+// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
@@ -139,35 +139,35 @@
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
-// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
-// Retrieval info: USED_PORT: rdusedw 0 0 8 0 OUTPUT NODEFVAL rdusedw[7..0]
+// Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL rdusedw[8..0]
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
-// Retrieval info: USED_PORT: wrusedw 0 0 8 0 OUTPUT NODEFVAL wrusedw[7..0]
-// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
-// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
+// Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL wrusedw[8..0]
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
-// Retrieval info: CONNECT: rdusedw 0 0 8 0 @rdusedw 0 0 8 0
+// Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-// Retrieval info: CONNECT: wrusedw 0 0 8 0 @wrusedw 0 0 8 0
+// Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k.v TRUE
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k_bb.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k_bb.v
2007-06-11 21:43:15 UTC (rev 5766)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k_bb.v
2007-06-11 23:38:59 UTC (rev 5767)
@@ -42,16 +42,16 @@
wrusedw);
input aclr;
- input [31:0] data;
+ input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
- output [31:0] q;
+ output [15:0] q;
output rdempty;
- output [7:0] rdusedw;
+ output [8:0] rdusedw;
output wrfull;
- output [7:0] wrusedw;
+ output [8:0] wrusedw;
endmodule
@@ -64,7 +64,7 @@
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
-// Retrieval info: PRIVATE: Depth NUMERIC "256"
+// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
@@ -76,7 +76,7 @@
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
-// Retrieval info: PRIVATE: Width NUMERIC "32"
+// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
@@ -90,35 +90,35 @@
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
-// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
-// Retrieval info: USED_PORT: rdusedw 0 0 8 0 OUTPUT NODEFVAL rdusedw[7..0]
+// Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL rdusedw[8..0]
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
-// Retrieval info: USED_PORT: wrusedw 0 0 8 0 OUTPUT NODEFVAL wrusedw[7..0]
-// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
-// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
+// Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL wrusedw[8..0]
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
-// Retrieval info: CONNECT: rdusedw 0 0 8 0 @rdusedw 0 0 8 0
+// Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-// Retrieval info: CONNECT: wrusedw 0 0 8 0 @wrusedw 0 0 8 0
+// Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k.v TRUE
Added:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_2k_1clk.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_2k_1clk.v
(rev 0)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_2k_1clk.v
2007-06-11 23:38:59 UTC (rev 5767)
@@ -0,0 +1,167 @@
+// megafunction wizard: %LPM_FIFO+%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: scfifo
+
+// ============================================================
+// File Name: fifo_2k_1clk.v
+// Megafunction Name(s):
+// scfifo
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2006 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module fifo_2k_1clk (
+ aclr,
+ clock,
+ data,
+ rdreq,
+ wrreq,
+ empty,
+ full,
+ q,
+ usedw);
+
+ input aclr;
+ input clock;
+ input [15:0] data;
+ input rdreq;
+ input wrreq;
+ output empty;
+ output full;
+ output [15:0] q;
+ output [9:0] usedw;
+
+ wire [9:0] sub_wire0;
+ wire sub_wire1;
+ wire [15:0] sub_wire2;
+ wire sub_wire3;
+ wire [9:0] usedw = sub_wire0[9:0];
+ wire empty = sub_wire1;
+ wire [15:0] q = sub_wire2[15:0];
+ wire full = sub_wire3;
+
+ scfifo scfifo_component (
+ .rdreq (rdreq),
+ .aclr (aclr),
+ .clock (clock),
+ .wrreq (wrreq),
+ .data (data),
+ .usedw (sub_wire0),
+ .empty (sub_wire1),
+ .q (sub_wire2),
+ .full (sub_wire3)
+ // synopsys translate_off
+ ,
+ .almost_empty (),
+ .sclr (),
+ .almost_full ()
+ // synopsys translate_on
+ );
+ defparam
+ scfifo_component.add_ram_output_register = "OFF",
+ scfifo_component.intended_device_family = "Cyclone",
+ scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
+ scfifo_component.lpm_numwords = 1024,
+ scfifo_component.lpm_showahead = "OFF",
+ scfifo_component.lpm_type = "scfifo",
+ scfifo_component.lpm_width = 16,
+ scfifo_component.lpm_widthu = 10,
+ scfifo_component.overflow_checking = "ON",
+ scfifo_component.underflow_checking = "ON",
+ scfifo_component.use_eab = "ON";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Depth NUMERIC "1024"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
+// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0]
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
+// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
+// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk.inc TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk.cmp TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk_wave*.jpg FALSE
Property changes on:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_2k_1clk.v
___________________________________________________________________
Name: svn:executable
+ *
Modified: gnuradio/branches/developers/thottelt/simulations/tx.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-06-11
21:43:15 UTC (rev 5766)
+++ gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-06-11
23:38:59 UTC (rev 5767)
@@ -243,53 +243,55 @@
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
-Project_Files_Count = 23
+Project_Files_Count = 24
Project_File_0 = ./strobe_gen_test.v
-Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
10 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177269906 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
10 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_1 = ./usb_fifo_writer_test.v
-Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181165989 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
14 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575397 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_2 = Z:/wc/inband/usrp/fpga/inband_lib/channel_ram.v
-Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181267786 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 21
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575398 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
21 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_3 = Z:/wc/simulations/data_packet_fifo_test.v
-Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 16
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575397 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
16 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_4 = Z:/wc/simulations/fake_tx_chain.v
-Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181267665 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575397 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
17 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_5 = Z:/wc/inband/usrp/fpga/megacells/fifo_2k.v
-Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727110 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 18
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232291 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 18
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_6 = Z:/wc/inband/usrp/fpga/sdr_lib/tx_chain.v
-Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726981 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 20
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232291 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 20
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_7 = ./fake_fx2_test.v
-Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727438 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
12 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177428969 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
12 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_8 = ./fake_fx2.v
-Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181183422 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
11 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_9 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
-Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181243950 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_10 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
-Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180995228 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 8
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_11 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
-Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181158584 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_12 = ../inband/usrp/fpga/inband_lib/usb_fifo_writer.v
-Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181267510 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
13 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_13 = ./chan_fifo_readers_test.v
-Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181074819 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 1
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_14 = ../inband/usrp/fpga/megacells/fifo_1k.v
-Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727110 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_15 = ./usb_packet_fifo_test.v
-Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_16 = Z:/wc/inband/usrp/fpga/sdr_lib/tx_buffer.v
-Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726979 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 19
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_17 = ./tx_buffer_test.v
-Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727438 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_18 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
-Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181008809 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_19 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
-Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726990 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 5
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_20 = ../inband/usrp/fpga/sdr_lib/strobe_gen.v
-Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726982 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_21 = Z:/wc/simulations/channel_ram_test.v
-Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181060194 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 22
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_22 = ./usb_fifo_reader_test.v
-Project_File_P_22 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727438 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575379 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_9 = Z:/wc/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
+Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181600463 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
23 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_10 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
+Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575461 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 6
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_11 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
+Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575398 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 8
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_12 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
+Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575398 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 4
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_13 = ../inband/usrp/fpga/inband_lib/usb_fifo_writer.v
+Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181591850 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
13 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_14 = ./chan_fifo_readers_test.v
+Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575379 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_15 = ../inband/usrp/fpga/megacells/fifo_1k.v
+Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181590269 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
15 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_16 = ./usb_packet_fifo_test.v
+Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177365360 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_17 = Z:/wc/inband/usrp/fpga/sdr_lib/tx_buffer.v
+Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232291 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 19
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_18 = ./tx_buffer_test.v
+Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1179008242 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_19 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
+Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575398 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 7
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_20 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
+Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232288 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 5
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_21 = ../inband/usrp/fpga/sdr_lib/strobe_gen.v
+Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232291 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_22 = Z:/wc/simulations/channel_ram_test.v
+Project_File_P_22 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575397 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
22 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_23 = ./usb_fifo_reader_test.v
+Project_File_P_23 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178397904 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2
cover_expr 0 dont_compile 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
@@ -319,6 +321,6 @@
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
-EditorState = {tabbed horizontal 0}
+EditorState = {tabbed horizontal 1}
{Z:/wc/inband/usrp/fpga/megacells/fifo_2k.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/rx_buffer_inband.v 0 1}
{Z:/wc/inband/usrp/fpga/megacells/fifo_1k.v 0 0}
{Z:/wc/inband/usrp/fpga/sdr_lib/rx_buffer.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/tx_buffer_inband.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/channel_ram.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/usb_fifo_writer.v 0 0}
Project_Major_Version = 6
Project_Minor_Version = 1
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- [Commit-gnuradio] r5767 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib inband/usrp/fpga/megacells simulations,
thottelt <=