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[Commit-gnuradio] r5785 - gnuradio/branches/developers/matt/u2f/sdr_lib


From: matt
Subject: [Commit-gnuradio] r5785 - gnuradio/branches/developers/matt/u2f/sdr_lib
Date: Sun, 17 Jun 2007 00:56:42 -0600 (MDT)

Author: matt
Date: 2007-06-17 00:56:42 -0600 (Sun, 17 Jun 2007)
New Revision: 5785

Modified:
   gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_rx.v
   gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_tx.v
Log:
compilation fixes


Modified: gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_rx.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_rx.v 2007-06-17 
06:55:48 UTC (rev 5784)
+++ gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_rx.v 2007-06-17 
06:56:42 UTC (rev 5785)
@@ -10,22 +10,26 @@
    output rx_write_o,
    output rx_done_o,
    input rx_ready_i,
-   input rx_full_i
+   input rx_full_i,
+   output overrun
    );
 
    wire [15:0] scale_i, scale_q;
    wire [31:0] phase_inc;
    reg [31:0]  phase;
+
+   wire [23:0] i_decim, q_decim;
+   wire [7:0]  decim_rate;
    
-   setting_reg #(.my_addr(1))
+   setting_reg #(.my_addr(1)) sr_0
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(phase_inc),.changed());
    
-   setting_reg #(.my_addr(2))
+   setting_reg #(.my_addr(2)) sr_1
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out({scale_i,scale_q}),.changed());
    
-   setting_reg #(.my_addr(3))
+   setting_reg #(.my_addr(3)) sr_2
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(decim_rate),.changed());
 
@@ -37,8 +41,8 @@
 
    wire [23:0] i_bb, q_bb;
    
-   strobe_gen (.clock(clk),.reset(rst),.enable(1'b1),.rate(decim_rate),
-              .strobe_in(1),.strobe(stb_decim) );
+   strobe_gen 
strobe_gen(.clock(clk),.reset(rst),.enable(1'b1),.rate(decim_rate),
+                        .strobe_in(1),.strobe(stb_decim) );
    
    cordic #(.bitwidth(24))
      cordic(.clock(clk), .reset(rst), .enable(1'b1),
@@ -61,7 +65,7 @@
    assign      overrun = full & stb_decim;
    
    shortfifo rxshortfifo
-     (.clk(clk),.rst(rst),.datain({i_decim,q_decim}),.dataout(rx_dat_o),
+     
(.clk(clk),.rst(rst),.datain({i_decim[23:8],q_decim[23:8]}),.dataout(rx_dat_o),
       .read(rx_write_o),.write(stb_decim & ~full),.full(full),.empty(empty));
    
 endmodule // dsp_core_rx

Modified: gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_tx.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_tx.v 2007-06-17 
06:55:48 UTC (rev 5784)
+++ gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_tx.v 2007-06-17 
06:56:42 UTC (rev 5785)
@@ -10,7 +10,8 @@
    output tx_read_o,
    output tx_done_o,
    input tx_ready_i,
-   input tx_empty_i
+   input tx_empty_i,
+   output underrun
    );
 
    wire [15:0] i, q, scale_i, scale_q;
@@ -23,15 +24,15 @@
    //  (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
    //   .in(set_data),.out({i,q}),.changed());
    
-   setting_reg #(.my_addr(1))
+   setting_reg #(.my_addr(1)) sr_0
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(phase_inc),.changed());
    
-   setting_reg #(.my_addr(2))
+   setting_reg #(.my_addr(2)) sr_1
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out({scale_i,scale_q}),.changed());
    
-   setting_reg #(.my_addr(3))
+   setting_reg #(.my_addr(3)) sr_2
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(interp_rate),.changed());
 
@@ -44,8 +45,8 @@
      (.clk(clk),.rst(rst),.datain(tx_dat_i),.dataout({i,q}),
       .read(stb_interp & ~empty),.write(tx_read_o),.full(full),.empty(empty));
 
-   strobe_gen (.clock(clk),.reset(rst),.enable(1'b1),.rate(interp_rate),
-              .strobe_in(1),.strobe(stb_interp) );
+   strobe_gen 
strobe_gen(.clock(clk),.reset(rst),.enable(1'b1),.rate(interp_rate),
+                        .strobe_in(1),.strobe(stb_interp) );
    
    always @(posedge clk)
      if(rst)
@@ -58,6 +59,8 @@
    
    wire         signed [35:0] prod_i, prod_q;
 
+   wire [15:0]          i_interp, q_interp;
+   
    cic_interp  #(.bw(16),.N(4),.log2_of_max_rate(7))
      cic_interp_i(.clock(clk),.reset(rst),.enable(1),.rate(interp_rate),
                  .strobe_in(stb_interp),.strobe_out(1),





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