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[Commit-gnuradio] r5787 - gnuradio/branches/developers/matt/u2f/models
From: |
matt |
Subject: |
[Commit-gnuradio] r5787 - gnuradio/branches/developers/matt/u2f/models |
Date: |
Sun, 17 Jun 2007 00:58:18 -0600 (MDT) |
Author: matt
Date: 2007-06-17 00:58:18 -0600 (Sun, 17 Jun 2007)
New Revision: 5787
Added:
gnuradio/branches/developers/matt/u2f/models/SRL16E.v
Modified:
gnuradio/branches/developers/matt/u2f/models/MULT18X18S.v
Log:
compilation fixes
Modified: gnuradio/branches/developers/matt/u2f/models/MULT18X18S.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/models/MULT18X18S.v 2007-06-17
06:57:24 UTC (rev 5786)
+++ gnuradio/branches/developers/matt/u2f/models/MULT18X18S.v 2007-06-17
06:58:18 UTC (rev 5787)
@@ -3,7 +3,7 @@
// As in the Spartan 3 series
module MULT18X18S
- (output signed [35:0] P,
+ (output reg signed [35:0] P,
input signed [17:0] A,
input signed [17:0] B,
input C, // Clock
Added: gnuradio/branches/developers/matt/u2f/models/SRL16E.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/models/SRL16E.v
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/models/SRL16E.v 2007-06-17
06:58:18 UTC (rev 5787)
@@ -0,0 +1,53 @@
+// $Header:
/devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/SRL16E.v,v
1.7 2005/03/14 22:32:58 yanx Exp $
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995/2004 Xilinx, Inc.
+// All Right Reserved.
+///////////////////////////////////////////////////////////////////////////////
+// ____ ____
+// / /\/ /
+// /___/ \ / Vendor : Xilinx
+// \ \ \/ Version : 8.1i (I.13)
+// \ \ Description : Xilinx Functional Simulation Library Component
+// / / 16-Bit Shift Register Look-Up-Table with Clock
Enable
+// /___/ /\ Filename : SRL16E.v
+// \ \ / \ Timestamp : Thu Mar 25 16:43:40 PST 2004
+// \___\/\___\
+//
+// Revision:
+// 03/23/04 - Initial version.
+// End Revision
+
+`timescale 1 ps / 1 ps
+
+
+module SRL16E (Q, A0, A1, A2, A3, CE, CLK, D);
+
+ parameter INIT = 16'h0000;
+
+ output Q;
+
+ input A0, A1, A2, A3, CE, CLK, D;
+
+ reg [15:0] data;
+
+
+ assign Q = data[{A3, A2, A1, A0}];
+
+ initial
+ begin
+ assign data = INIT;
+ while (CLK === 1'b1 || CLK===1'bX)
+ #10;
+ deassign data;
+ end
+
+ always @(posedge CLK)
+ begin
+ if (CE == 1'b1) begin
+ {data[15:0]} <= #100 {data[14:0], D};
+ end
+ end
+
+
+endmodule
+
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