[Commit-gnuradio] r5803 - gnuradio/branches/developers/matt/u2f/control_lib

[matt]

Author: matt
Date: 2007-06-20 12:43:08 -0600 (Wed, 20 Jun 2007)
New Revision: 5803

Modified:
   gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
Log:
fix timing error (data read on wb was late)


Modified: gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v     
2007-06-20 05:02:37 UTC (rev 5802)
+++ gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v     
2007-06-20 18:43:08 UTC (rev 5803)
@@ -31,15 +31,16 @@
    // Write Interfaces
    input [31:0] wr0_dat_i, input wr0_write_i, input wr0_done_i, output 
wr0_ready_o, output wr0_full_o,
    input [31:0] wr1_dat_i, input wr1_write_i, input wr1_done_i, output 
wr1_ready_o, output wr1_full_o,
+   input [31:0] wr2_dat_i, input wr2_write_i, input wr2_done_i, output 
wr2_ready_o, output wr2_full_o,
+   input [31:0] wr3_dat_i, input wr3_write_i, input wr3_done_i, output 
wr3_ready_o, output wr3_full_o,
    
    // Read Interfaces
    output [31:0] rd0_dat_o, input rd0_read_i, input rd0_done_i, output 
rd0_ready_o, output rd0_empty_o,
-   output [31:0] rd1_dat_o, input rd1_read_i, input rd1_done_i, output 
rd1_ready_o, output rd1_empty_o
+   output [31:0] rd1_dat_o, input rd1_read_i, input rd1_done_i, output 
rd1_ready_o, output rd1_empty_o,
+   output [31:0] rd2_dat_o, input rd2_read_i, input rd2_done_i, output 
rd2_ready_o, output rd2_empty_o,
+   output [31:0] rd3_dat_o, input rd3_read_i, input rd3_done_i, output 
rd3_ready_o, output rd3_empty_o
    );
 
-   assign wb_err_o = 1'b0;  // Unused for now
-   assign wb_rty_o = 1'b0;  // Unused for now
-
    wire [7:0] sel_a;
 
    wire [2:0]  which_buf = wb_adr_i[13:11];   // address 15:14 selects the 
buffer pool
@@ -88,7 +89,7 @@
           setting_reg #(.my_addr(i)) 
             
sreg(.clk(stream_clk),.rst(stream_rst),.strobe(set_stb),.addr(set_addr),.in(set_data),
                  
.out({dummy[i],read_port[i],write_port[i],write_go[i],read_go[i],step[i],ll[i],fl[i]}),.changed(changed[i]));
-          buffer_2k buffer_2k
+          ram_2port #(.DWIDTH(32),.AWIDTH(9)) buffer
             (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[i]),.wea(wb_we_i),
              .addra(buf_addra),.dia(wb_dat_i),.doa(buf_doa[i]),
              
.clkb(stream_clk),.enb(buf_enb[i]),.web(buf_web[i]),.addrb(buf_addrb[i]),.dib(buf_dib[i]),.dob(buf_dob[i]));
 
@@ -113,14 +114,20 @@
              );
        end
    endgenerate
+
+   // Wishbone Outputs
+   always @*
+     wb_dat_o <= buf_doa[which_buf];
+
+   //always @(posedge wb_clk_i)
+   //  if(wb_stb_i)
+   //    wb_dat_o <= buf_doa[which_buf];
    
    always @(posedge wb_clk_i)
-     if(wb_stb_i)
-       wb_dat_o <= buf_doa[which_buf];
-   
-   
-   always @(posedge wb_clk_i)
      wb_ack_o <= wb_stb_i;
    
+   assign wb_err_o = 1'b0;  // Unused for now
+   assign wb_rty_o = 1'b0;  // Unused for now
+
 endmodule // buffer_pool