[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Commit-gnuradio] r5816 - in gnuradio/branches/developers/thottelt: inba
|
From: |
thottelt |
|
Subject: |
[Commit-gnuradio] r5816 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib inband/usrp/fpga/megacells inband/usrp/fpga/toplevel/usrp_inband_usb simulations simulations/work |
|
Date: |
Sat, 23 Jun 2007 09:10:09 -0600 (MDT) |
Author: thottelt
Date: 2007-06-23 09:10:08 -0600 (Sat, 23 Jun 2007)
New Revision: 5816
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/packet_builder.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.bsf
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k_bb.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
gnuradio/branches/developers/thottelt/simulations/rx_fake_fx2.v
gnuradio/branches/developers/thottelt/simulations/tx.mpf
gnuradio/branches/developers/thottelt/simulations/work/_info
Log:
working rx_inband (with only one channel) :)
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/packet_builder.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/packet_builder.v
2007-06-23 15:03:58 UTC (rev 5815)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/packet_builder.v
2007-06-23 15:10:08 UTC (rev 5816)
@@ -42,64 +42,65 @@
if (reset)
begin
WR <= 0;
- rd_select <= 0;
+ rd_select[0] <= 1;
+ rd_select[1] <= 0;
+ rd_select[2] <= 0;
chan_rdreq <= 0;
tstamp_complete <= 0;
state <= IDLE;
end
else case (state)
IDLE: begin
- rd_select[0] <= 1;
if (~chan_empty[0] && have_space)
- state <= HEADER1;
+ state <= #1 HEADER1;
end
HEADER1: begin
- fifodata[`PAYLOAD_LEN] <= (chan_usedw > 9'd252
+ fifodata[`PAYLOAD_LEN] <= #1 (chan_usedw > 9'd252
? 9'd252 : chan_usedw << 1);
- payload_len <= (chan_usedw > 9'd252
+ payload_len <= #1 (chan_usedw > 9'd252
? 9'd252 : chan_usedw << 1);
- fifodata[`TAG] <= 0;
- fifodata[`MBZ] <= 0;
- WR <= 1;
+ fifodata[`TAG] <= #1 0;
+ fifodata[`MBZ] <= #1 0;
+ WR <= #1 1;
- state <= HEADER2;
- read_length <= 0;
+ state <= #1 HEADER2;
+ read_length <= #1 0;
end
HEADER2: begin
- fifodata[`CHAN] <= 0;
- fifodata[`RSSI] <= 0;
- fifodata[`BURST] <= 0;
- fifodata[`DROPPED] <= 0;
- fifodata[`UNDERRUN] <= 0;
- fifodata[`OVERRUN] <= 0;
+ fifodata[`CHAN] <= #1 0;
+ fifodata[`RSSI] <= #1 0;
+ fifodata[`BURST] <= #1 0;
+ fifodata[`DROPPED] <= #1 0;
+ fifodata[`UNDERRUN] <= #1 0;
+ fifodata[`OVERRUN] <= #1 0;
- state <= TIMESTAMP;
+ state <= #1 TIMESTAMP;
end
TIMESTAMP: begin
- fifodata <= 0;
- tstamp_complete <= ~tstamp_complete;
+ fifodata <= #1 16'd0;
+ tstamp_complete <= #1 ~tstamp_complete;
if (~tstamp_complete)
- chan_rdreq[0] <= 1;
+ chan_rdreq[0] <= #1 1;
- state <= (tstamp_complete ? FORWARD : TIMESTAMP);
+ state <= #1 (tstamp_complete ? FORWARD : TIMESTAMP);
end
FORWARD: begin
- read_length <= read_length + 9'd2;
- fifodata <= (read_length >= payload_len ? 16'hDEAD :
chan_fifodata);
+ read_length <= #1 read_length + 9'd2;
+ fifodata <= #1 (read_length >= payload_len ? 16'hDEAD :
chan_fifodata);
- if (read_length == `MAXPAYLOAD)
+ if (read_length >= `MAXPAYLOAD)
begin
- WR <= 0;
- state <= IDLE;
+ WR <= #1 0;
+ state <= #1 IDLE;
end
else if (read_length == payload_len - 4)
- chan_rdreq <= 0;
+ chan_rdreq <= #1 0;
end
default: begin
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2007-06-23 15:03:58 UTC (rev 5815)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2007-06-23 15:10:08 UTC (rev 5816)
@@ -47,8 +47,8 @@
wire [15:0] fifodata;
wire WR;
wire have_space;
-
- fifo_1k rx_usb_fifo (
+
+ fifo_4k rx_usb_fifo (
.aclr ( reset ),
.data ( fifodata ),
.rdclk ( ~usbclk ),
@@ -61,8 +61,8 @@
.wrfull ( ),
.wrusedw ( wrusedw ) );
- assign have_pkt_rdy = (rdusedw >= 256);
- assign have_space = (wrusedw < 256);
+ assign have_pkt_rdy = (rdusedw >= 256);
+ assign have_space = (wrusedw < 760);
// Rx side fifos
wire [NUM_CHAN:0] chan_rdreq;
@@ -88,37 +88,44 @@
always @(posedge rxclk)
if(reset)
rx_overrun <= 1'b0;
- else if(rx_full[0] || rx_full[1])
+ else if(rx_full[0])
rx_overrun <= 1'b1;
else if(clear_status)
rx_overrun <= 1'b0;
- /* TODO write this genericly */
+ reg [15:0] test;
+ always @(posedge rxclk)
+ if (reset)
+ test <= 0;
+ else if (~rx_full[0])
+ test <= test + 1;
+
+ // TODO write this genericly
wire [15:0]ch[NUM_CHAN:0];
assign ch[0] = ch_0;
- assign ch[1] = ch_1;
+ assign ch[1] = ch_1;
generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
- begin : generate_channel_fifos
+ begin : generate_channel_fifos
wire [15:0] dataout;
wire [9:0] usedw;
assign chan_fifodata = (rd_select[i] ? dataout : 16'bZ);
assign chan_usedw = (rd_select[i] ? usedw : 10'bZ);
- assign chan_empty[i] = usedw < 10'd2;
-
+ assign chan_empty[i] = usedw < 10'd126;
+
fifo_2k_1clk rx_chan_fifo (
.aclr ( reset ),
.clock ( rxclk ),
.data ( ch[i] ),
.rdreq ( chan_rdreq[i] ),
- .wrreq ( ~rx_full[i] & rxstrobe & (i==0)),
+ .wrreq ( ~rx_full[i] & rxstrobe ),
.empty ( ),
.full ( rx_full[i] ),
.q ( dataout ),
- .usedw ( usedw ) );
- end
- endgenerate
+ .usedw ( usedw ) );
+ end
+ endgenerate
- assign debugbus = 0;
+ assign debugbus = 0;
endmodule
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.bsf
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.bsf
2007-06-23 15:03:58 UTC (rev 5815)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.bsf
2007-06-23 15:10:08 UTC (rev 5816)
@@ -101,6 +101,7 @@
(line (pt 160 136)(pt 144 136)(line_width 3))
)
(drawing
+ (text "(ack)" (rect 51 99 72 111)(font "Arial" ))
(text "16 bits x 512 words" (rect 63 156 144 168)(font "Arial"
))
(line (pt 16 16)(pt 144 16)(line_width 1))
(line (pt 144 16)(pt 144 168)(line_width 1))
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.v
===================================================================
--- gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.v
2007-06-23 15:03:58 UTC (rev 5815)
+++ gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k.v
2007-06-23 15:10:08 UTC (rev 5816)
@@ -93,7 +93,7 @@
dcfifo_component.intended_device_family = "Cyclone",
dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
dcfifo_component.lpm_numwords = 512,
- dcfifo_component.lpm_showahead = "OFF",
+ dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 16,
dcfifo_component.lpm_widthu = 9,
@@ -118,7 +118,7 @@
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
@@ -140,7 +140,7 @@
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
-// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k_bb.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k_bb.v
2007-06-23 15:03:58 UTC (rev 5815)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_1k_bb.v
2007-06-23 15:10:08 UTC (rev 5816)
@@ -69,7 +69,7 @@
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
@@ -91,7 +91,7 @@
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
-// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-06-23 15:03:58 UTC (rev 5815)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-06-23 15:10:08 UTC (rev 5816)
@@ -19,8 +19,8 @@
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
-`define TX_IN_BAND
-//`define RX_IN_BAND
+//`define TX_IN_BAND
+`define RX_IN_BAND
`include "config.vh"
`include "../../../firmware/include/fpga_regs_common.v"
Modified: gnuradio/branches/developers/thottelt/simulations/rx_fake_fx2.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/rx_fake_fx2.v
2007-06-23 15:03:58 UTC (rev 5815)
+++ gnuradio/branches/developers/thottelt/simulations/rx_fake_fx2.v
2007-06-23 15:10:08 UTC (rev 5816)
@@ -42,7 +42,7 @@
.clock(rxclk),
.reset(reset),
.enable(SEN),
- .rate(8'd4),
+ .rate(8'd15),
.strobe_in(1'd1),
.strobe(rxstrobe) );
@@ -84,7 +84,7 @@
IDLE: begin
if (have_pkt_rdy)
begin
- state <= WAIT;
+ state <= RCV;
RD <= 1;
count <= 0;
end
Modified: gnuradio/branches/developers/thottelt/simulations/tx.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-06-23
15:03:58 UTC (rev 5815)
+++ gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-06-23
15:10:08 UTC (rev 5816)
@@ -262,44 +262,44 @@
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177428969 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_8 = ./fake_fx2.v
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575379 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
11 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_9 = Z:/wc/inband/usrp/fpga/inband_lib/packet_builder.v
-Project_File_P_9 = vlog_protect 0 cover_toggle 0 vhdl_novitalcheck 0
cover_exttoggle 0 file_type verilog group_id 0 vhdl_nodebug 0 vhdl_1164 1
cover_cond 0 vhdl_noload 0 vlog_1995compat 0 vlog_nodebug 0 vhdl_synth 0
vhdl_enable0In 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile
1181926751 vhdl_disableopt 0 vlog_enable0In 0 vhdl_vital 0 vlog_disableopt 0
vhdl_vopt 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0
vlog_vopt 0 vlog_optionfile Z:/wc/simulations/vlog.opt vhdl_warn3 1
vhdl_0InOptions {} vlog_showsource 0 vlog_hazard 0 vhdl_warn4 1 vhdl_options {}
vlog_0InOptions {} vhdl_warn5 1 ood 0 vlog_options {} vlog_upper 0 compile_to
work compile_order 24 cover_expr 0 cover_nosub 0 dont_compile 0 cover_stmt 0
vhdl_use93 2002
-Project_File_10 = Z:/wc/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
-Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1182198467 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 23
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_11 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
-Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575461 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_12 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
-Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575398 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 8
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_9 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
+Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575398 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 8
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_10 = Z:/wc/inband/usrp/fpga/inband_lib/packet_builder.v
+Project_File_P_10 = vlog_protect 0 cover_toggle 0 vhdl_novitalcheck 0
cover_exttoggle 0 file_type verilog group_id 0 vhdl_nodebug 0 vhdl_1164 1
cover_cond 0 vhdl_noload 0 vhdl_enable0In 0 vhdl_synth 0 vlog_1995compat 0
vlog_nodebug 0 vhdl_disableopt 0 last_compile 1182367979 folder {Top Level}
cover_branch 0 vlog_noload 0 vhdl_vital 0 vlog_enable0In 0 vhdl_warn1 1
vhdl_vopt 0 vlog_disableopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1
vhdl_0InOptions {} vhdl_warn3 1 vlog_optionfile Z:/wc/simulations/vlog.opt
vlog_vopt 0 vhdl_options {} vhdl_warn4 1 vlog_hazard 0 vlog_showsource 0 ood 0
vhdl_warn5 1 vlog_0InOptions {} compile_to work vlog_upper 0 vlog_options {}
compile_order 24 dont_compile 0 cover_nosub 0 cover_expr 0 vhdl_use93 2002
cover_stmt 0
+Project_File_11 = Z:/wc/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
+Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1182367408 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 23
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_12 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
+Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575461 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_13 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575398 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_14 = ../inband/usrp/fpga/inband_lib/usb_fifo_writer.v
-Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181591850 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_15 = ./chan_fifo_readers_test.v
-Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575379 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 1
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_14 = ./chan_fifo_readers_test.v
+Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575379 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 1
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_15 = ../inband/usrp/fpga/inband_lib/usb_fifo_writer.v
+Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181591850 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_16 = ../inband/usrp/fpga/megacells/fifo_1k.v
-Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181590269 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_17 = ./usb_packet_fifo_test.v
-Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177365360 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 0
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_18 = Z:/wc/inband/usrp/fpga/sdr_lib/tx_buffer.v
-Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232291 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
19 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_19 = ./tx_buffer_test.v
-Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1179008242 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 3
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1182351098 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
15 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_17 = Z:/wc/inband/usrp/fpga/sdr_lib/tx_buffer.v
+Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232291 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
19 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_18 = ./usb_packet_fifo_test.v
+Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177365360 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 0
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_19 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
+Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232288 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_20 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575398 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_21 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
-Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232288 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_22 = Z:/wc/simulations/rx_chains.v
-Project_File_P_22 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181852410 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 26
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_23 = Z:/wc/simulations/rx_fake_fx2.v
-Project_File_P_23 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181863921 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
25 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_24 = ../inband/usrp/fpga/sdr_lib/strobe_gen.v
-Project_File_P_24 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232291 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 9
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_25 = Z:/wc/simulations/channel_ram_test.v
-Project_File_P_25 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575397 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 22
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_26 = Z:/wc/inband/usrp/fpga/megacells/fifo_2k_1clk.v
-Project_File_P_26 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181850595 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
27 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_27 = ./usb_fifo_reader_test.v
-Project_File_P_27 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178397904 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 2
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_21 = ./tx_buffer_test.v
+Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1179008242 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 3
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_22 = Z:/wc/simulations/channel_ram_test.v
+Project_File_P_22 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575397 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 22
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_23 = ../inband/usrp/fpga/sdr_lib/strobe_gen.v
+Project_File_P_23 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232291 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 9
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_24 = Z:/wc/simulations/rx_fake_fx2.v
+Project_File_P_24 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1182363783 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 25
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_25 = Z:/wc/simulations/rx_chains.v
+Project_File_P_25 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181852410 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 26
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_26 = ./usb_fifo_reader_test.v
+Project_File_P_26 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178397904 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 2
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_27 = Z:/wc/inband/usrp/fpga/megacells/fifo_2k_1clk.v
+Project_File_P_27 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181850595 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
27 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
@@ -329,6 +329,6 @@
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
-EditorState = {tabbed horizontal 1}
{Z:/wc/inband/usrp/fpga/inband_lib/rx_buffer_inband.v 0 1}
{Z:/wc/inband/usrp/fpga/inband_lib/packet_builder.v 0 0}
{Z:/wc/simulations/rx_fake_fx2.v 0 0}
+EditorState = {tabbed horizontal 1} {Z:/wc/simulations/rx_fake_fx2.v 0 1}
{Z:/wc/inband/usrp/fpga/inband_lib/rx_buffer_inband.v 0 0}
Project_Major_Version = 6
Project_Minor_Version = 1
Modified: gnuradio/branches/developers/thottelt/simulations/work/_info
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/work/_info
2007-06-23 15:03:58 UTC (rev 5815)
+++ gnuradio/branches/developers/thottelt/simulations/work/_info
2007-06-23 15:10:08 UTC (rev 5816)
@@ -603,10 +603,10 @@
o-work work -O0
tGenerateLoopIterationMax 100000
vfifo_1k
-I1=Y_O]g[elLTn;_;IMc<<3
+I`lMV2?1OMnOMBRaAI5fgL1
address@hidden@eD71
dZ:\wc\simulations
-w1181590269
+w1182351098
F../inband/usrp/fpga/megacells/fifo_1k.v
L0 36
address@hidden@eD71
@@ -1101,10 +1101,10 @@
tGenerateLoopIterationMax 100000
address@hidden@f_stratixii_pll
vpacket_builder
-IN6la^ACW]oE[MW<H?M1dO2
+IG;PmTkYeCCRaRJ9PI`^782
VKa]1?4R;5jIeg<_:nF7Ya3
dZ:\wc\simulations
-w1181926751
+w1182367979
FZ:/wc/inband/usrp/fpga/inband_lib/packet_builder.v
L0 1
VKa]1?4R;5jIeg<_:nF7Ya3
@@ -1140,10 +1140,10 @@
o-work work -O0
tGenerateLoopIterationMax 100000
vrx_buffer_inband
-IbL<:8Rea0<Aj`=8_S8hZ=0
+IUn3Rc[mogO^cAFhQH^T_H1
V>address@hidden
dZ:\wc\simulations
-w1182198467
+w1182367408
FZ:/wc/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
L0 4
V>address@hidden
@@ -1166,10 +1166,10 @@
o-work work -O0
tGenerateLoopIterationMax 100000
vrx_fake_fx2
-I[SMU<dW[c4PojT7AWHc643
+IngJk0L;L58jJ3>:address@hidden
V<Zz<:address@hidden:=9n>O:i3
dZ:\wc\simulations
-w1181863921
+w1182363783
FZ:/wc/simulations/rx_fake_fx2.v
L0 1
V<Zz<:address@hidden:=9n>O:i3
| [Prev in Thread] |
Current Thread |
[Next in Thread] |
- [Commit-gnuradio] r5816 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib inband/usrp/fpga/megacells inband/usrp/fpga/toplevel/usrp_inband_usb simulations simulations/work,
thottelt <=