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[Commit-gnuradio] r5818 - gnuradio/branches/developers/thottelt/inband/u
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From: |
thottelt |
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Subject: |
[Commit-gnuradio] r5818 - gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib |
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Date: |
Sat, 23 Jun 2007 10:32:43 -0600 (MDT) |
Author: thottelt
Date: 2007-06-23 10:32:43 -0600 (Sat, 23 Jun 2007)
New Revision: 5818
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/packet_builder.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
Log:
RX: timestamps corrected
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/packet_builder.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/packet_builder.v
2007-06-23 15:11:53 UTC (rev 5817)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/packet_builder.v
2007-06-23 16:32:43 UTC (rev 5818)
@@ -1,113 +1,114 @@
-module packet_builder #(parameter NUM_CHAN = 2) (
- // System
- input rxclk,
- input reset,
- // ADC side
- input [15:0]chan_fifodata,
- input [NUM_CHAN:0]chan_empty,
- input [9:0]chan_usedw,
- output reg [NUM_CHAN:0]rd_select,
- output reg [NUM_CHAN:0]chan_rdreq,
- // FX2 side
- output reg WR,
- output reg [15:0]fifodata,
- input have_space );
-
- parameter IDLE = 0;
- parameter HEADER1 = 1;
- parameter HEADER2 = 2;
- parameter TIMESTAMP = 3;
- parameter FORWARD = 4;
-
- `define MAXPAYLOAD 504
-
- `define PAYLOAD_LEN 8:0
- `define TAG 12:9
- `define MBZ 15:13
-
- `define CHAN 4:0
- `define RSSI 10:5
- `define BURST 12:11
- `define DROPPED 13
- `define UNDERRUN 14
- `define OVERRUN 15
-
- reg [3:0] state;
- reg [8:0] read_length;
- reg [8:0] payload_len;
- reg tstamp_complete;
-
- always @(posedge rxclk)
- begin
- if (reset)
- begin
- WR <= 0;
- rd_select[0] <= 1;
- rd_select[1] <= 0;
- rd_select[2] <= 0;
- chan_rdreq <= 0;
- tstamp_complete <= 0;
- state <= IDLE;
- end
- else case (state)
- IDLE: begin
-
- if (~chan_empty[0] && have_space)
- state <= #1 HEADER1;
- end
-
- HEADER1: begin
- fifodata[`PAYLOAD_LEN] <= #1 (chan_usedw > 9'd252
- ? 9'd252 : chan_usedw << 1);
- payload_len <= #1 (chan_usedw > 9'd252
- ? 9'd252 : chan_usedw << 1);
- fifodata[`TAG] <= #1 0;
- fifodata[`MBZ] <= #1 0;
- WR <= #1 1;
-
- state <= #1 HEADER2;
- read_length <= #1 0;
- end
-
- HEADER2: begin
- fifodata[`CHAN] <= #1 0;
- fifodata[`RSSI] <= #1 0;
- fifodata[`BURST] <= #1 0;
- fifodata[`DROPPED] <= #1 0;
- fifodata[`UNDERRUN] <= #1 0;
- fifodata[`OVERRUN] <= #1 0;
-
- state <= #1 TIMESTAMP;
- end
-
- TIMESTAMP: begin
- fifodata <= #1 16'd0;
- tstamp_complete <= #1 ~tstamp_complete;
-
- if (~tstamp_complete)
- chan_rdreq[0] <= #1 1;
-
- state <= #1 (tstamp_complete ? FORWARD : TIMESTAMP);
- end
-
- FORWARD: begin
- read_length <= #1 read_length + 9'd2;
- fifodata <= #1 (read_length >= payload_len ? 16'hDEAD :
chan_fifodata);
-
- if (read_length >= `MAXPAYLOAD)
- begin
- WR <= #1 0;
- state <= #1 IDLE;
- end
- else if (read_length == payload_len - 4)
- chan_rdreq <= #1 0;
- end
-
- default: begin
- $display("error unknown state");
- state <= IDLE;
- end
- endcase
- end
-endmodule
-
+module packet_builder #(parameter NUM_CHAN = 2) (
+ // System
+ input rxclk,
+ input reset,
+ input [31:0] adctime,
+ // ADC side
+ input [15:0]chan_fifodata,
+ input [NUM_CHAN:0]chan_empty,
+ input [9:0]chan_usedw,
+ output reg [NUM_CHAN:0]rd_select,
+ output reg [NUM_CHAN:0]chan_rdreq,
+ // FX2 side
+ output reg WR,
+ output reg [15:0]fifodata,
+ input have_space );
+
+ parameter IDLE = 0;
+ parameter HEADER1 = 1;
+ parameter HEADER2 = 2;
+ parameter TIMESTAMP = 3;
+ parameter FORWARD = 4;
+
+ `define MAXPAYLOAD 504
+
+ `define PAYLOAD_LEN 8:0
+ `define TAG 12:9
+ `define MBZ 15:13
+
+ `define CHAN 4:0
+ `define RSSI 10:5
+ `define BURST 12:11
+ `define DROPPED 13
+ `define UNDERRUN 14
+ `define OVERRUN 15
+
+ reg [3:0] state;
+ reg [8:0] read_length;
+ reg [8:0] payload_len;
+ reg tstamp_complete;
+
+ always @(posedge rxclk)
+ begin
+ if (reset)
+ begin
+ WR <= 0;
+ rd_select[0] <= 1;
+ rd_select[1] <= 0;
+ rd_select[2] <= 0;
+ chan_rdreq <= 0;
+ tstamp_complete <= 0;
+ state <= IDLE;
+ end
+ else case (state)
+ IDLE: begin
+
+ if (~chan_empty[0] && have_space)
+ state <= #1 HEADER1;
+ end
+
+ HEADER1: begin
+ fifodata[`PAYLOAD_LEN] <= #1 (chan_usedw > 9'd252
+ ? 9'd252 : chan_usedw << 1);
+ payload_len <= #1 (chan_usedw > 9'd252
+ ? 9'd252 : chan_usedw << 1);
+ fifodata[`TAG] <= #1 0;
+ fifodata[`MBZ] <= #1 0;
+ WR <= #1 1;
+
+ state <= #1 HEADER2;
+ read_length <= #1 0;
+ end
+
+ HEADER2: begin
+ fifodata[`CHAN] <= #1 0;
+ fifodata[`RSSI] <= #1 0;
+ fifodata[`BURST] <= #1 0;
+ fifodata[`DROPPED] <= #1 0;
+ fifodata[`UNDERRUN] <= #1 0;
+ fifodata[`OVERRUN] <= #1 0;
+
+ state <= #1 TIMESTAMP;
+ end
+
+ TIMESTAMP: begin
+ fifodata <= #1 (tstamp_complete ? adctime[31:16] :
adctime[15:0]);
+ tstamp_complete <= #1 ~tstamp_complete;
+
+ if (~tstamp_complete)
+ chan_rdreq[0] <= #1 1;
+
+ state <= #1 (tstamp_complete ? FORWARD : TIMESTAMP);
+ end
+
+ FORWARD: begin
+ read_length <= #1 read_length + 9'd2;
+ fifodata <= #1 (read_length >= payload_len ? 16'hDEAD :
chan_fifodata);
+
+ if (read_length >= `MAXPAYLOAD)
+ begin
+ WR <= #1 0;
+ state <= #1 IDLE;
+ end
+ else if (read_length == payload_len - 4)
+ chan_rdreq <= #1 0;
+ end
+
+ default: begin
+ $display("error unknown state");
+ state <= IDLE;
+ end
+ endcase
+ end
+endmodule
+
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2007-06-23 15:11:53 UTC (rev 5817)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2007-06-23 16:32:43 UTC (rev 5818)
@@ -1,131 +1,140 @@
-//`include "../../firmware/include/fpga_regs_common.v"
-//`include "../../firmware/include/fpga_regs_standard.v"
-
-module rx_buffer_inband
- ( input usbclk,
- input bus_reset,
- input reset, // DSP side reset (used here), do not reset registers
- input reset_regs, //Only reset registers
- output [15:0] usbdata,
- input RD,
- output wire have_pkt_rdy,
- output reg rx_overrun,
- input wire [3:0] channels,
- input wire [15:0] ch_0,
- input wire [15:0] ch_1,
- input wire [15:0] ch_2,
- input wire [15:0] ch_3,
- input wire [15:0] ch_4,
- input wire [15:0] ch_5,
- input wire [15:0] ch_6,
- input wire [15:0] ch_7,
- input rxclk,
- input rxstrobe,
- input clear_status,
- input [6:0] serial_addr,
- input [31:0] serial_data,
- input serial_strobe,
- output [15:0] debugbus
- );
-
- parameter NUM_CHAN = 2;
- genvar i ;
-
- // FX2 Bug Fix
- reg [8:0] read_count;
- always @(negedge usbclk)
- if(bus_reset)
- read_count <= #1 9'd0;
- else if(RD & ~read_count[8])
- read_count <= #1 read_count + 9'd1;
- else
- read_count <= #1 RD ? read_count : 9'b0;
-
- // USB side fifo
- wire [8:0] rdusedw;
- wire [8:0] wrusedw;
- wire [15:0] fifodata;
- wire WR;
- wire have_space;
-
- fifo_4k rx_usb_fifo (
- .aclr ( reset ),
- .data ( fifodata ),
- .rdclk ( ~usbclk ),
- .rdreq ( RD & ~read_count[8] ),
- .wrclk ( rxclk ),
- .wrreq ( WR ),
- .q ( usbdata ),
- .rdempty ( ),
- .rdusedw ( rdusedw ),
- .wrfull ( ),
- .wrusedw ( wrusedw ) );
-
- assign have_pkt_rdy = (rdusedw >= 256);
- assign have_space = (wrusedw < 760);
-
- // Rx side fifos
- wire [NUM_CHAN:0] chan_rdreq;
- wire [15:0] chan_fifodata;
- wire [9:0] chan_usedw;
- wire [NUM_CHAN:0] chan_empty;
- wire [NUM_CHAN:0] rd_select;
- wire [NUM_CHAN:0] rx_full;
-
- packet_builder #(NUM_CHAN) rx_pkt_builer (
- .rxclk ( rxclk ),
- .reset ( reset ),
- .chan_rdreq ( chan_rdreq ),
- .chan_fifodata ( chan_fifodata ),
- .chan_empty ( chan_empty ),
- .rd_select ( rd_select ),
- .chan_usedw ( chan_usedw ),
- .WR ( WR ),
- .fifodata ( fifodata ),
- .have_space ( have_space ) );
-
- // Detect overrun
- always @(posedge rxclk)
- if(reset)
- rx_overrun <= 1'b0;
- else if(rx_full[0])
- rx_overrun <= 1'b1;
- else if(clear_status)
- rx_overrun <= 1'b0;
-
- reg [15:0] test;
- always @(posedge rxclk)
- if (reset)
- test <= 0;
- else if (~rx_full[0])
- test <= test + 1;
-
- // TODO write this genericly
- wire [15:0]ch[NUM_CHAN:0];
- assign ch[0] = ch_0;
- assign ch[1] = ch_1;
-
- generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
- begin : generate_channel_fifos
- wire [15:0] dataout;
- wire [9:0] usedw;
-
- assign chan_fifodata = (rd_select[i] ? dataout : 16'bZ);
- assign chan_usedw = (rd_select[i] ? usedw : 10'bZ);
- assign chan_empty[i] = usedw < 10'd126;
-
- fifo_2k_1clk rx_chan_fifo (
- .aclr ( reset ),
- .clock ( rxclk ),
- .data ( ch[i] ),
- .rdreq ( chan_rdreq[i] ),
- .wrreq ( ~rx_full[i] & rxstrobe ),
- .empty ( ),
- .full ( rx_full[i] ),
- .q ( dataout ),
- .usedw ( usedw ) );
- end
- endgenerate
-
- assign debugbus = 0;
-endmodule
+//`include "../../firmware/include/fpga_regs_common.v"
+//`include "../../firmware/include/fpga_regs_standard.v"
+
+module rx_buffer_inband
+ ( input usbclk,
+ input bus_reset,
+ input reset, // DSP side reset (used here), do not reset registers
+ input reset_regs, //Only reset registers
+ output [15:0] usbdata,
+ input RD,
+ output wire have_pkt_rdy,
+ output reg rx_overrun,
+ input wire [3:0] channels,
+ input wire [15:0] ch_0,
+ input wire [15:0] ch_1,
+ input wire [15:0] ch_2,
+ input wire [15:0] ch_3,
+ input wire [15:0] ch_4,
+ input wire [15:0] ch_5,
+ input wire [15:0] ch_6,
+ input wire [15:0] ch_7,
+ input rxclk,
+ input rxstrobe,
+ input clear_status,
+ input [6:0] serial_addr,
+ input [31:0] serial_data,
+ input serial_strobe,
+ output [15:0] debugbus
+ );
+
+ parameter NUM_CHAN = 2;
+ genvar i ;
+
+ // FX2 Bug Fix
+ reg [8:0] read_count;
+ always @(negedge usbclk)
+ if(bus_reset)
+ read_count <= #1 9'd0;
+ else if(RD & ~read_count[8])
+ read_count <= #1 read_count + 9'd1;
+ else
+ read_count <= #1 RD ? read_count : 9'b0;
+
+ // Time counter
+ reg [31:0] adctime;
+ always @(posedge rxclk)
+ if (reset)
+ adctime <= 0;
+ else if (rxstrobe)
+ adctime <= adctime + 1;
+
+ // USB side fifo
+ wire [8:0] rdusedw;
+ wire [8:0] wrusedw;
+ wire [15:0] fifodata;
+ wire WR;
+ wire have_space;
+
+ fifo_4k rx_usb_fifo (
+ .aclr ( reset ),
+ .data ( fifodata ),
+ .rdclk ( ~usbclk ),
+ .rdreq ( RD & ~read_count[8] ),
+ .wrclk ( rxclk ),
+ .wrreq ( WR ),
+ .q ( usbdata ),
+ .rdempty ( ),
+ .rdusedw ( rdusedw ),
+ .wrfull ( ),
+ .wrusedw ( wrusedw ) );
+
+ assign have_pkt_rdy = (rdusedw >= 256);
+ assign have_space = (wrusedw < 760);
+
+ // Rx side fifos
+ wire [NUM_CHAN:0] chan_rdreq;
+ wire [15:0] chan_fifodata;
+ wire [9:0] chan_usedw;
+ wire [NUM_CHAN:0] chan_empty;
+ wire [NUM_CHAN:0] rd_select;
+ wire [NUM_CHAN:0] rx_full;
+
+ packet_builder #(NUM_CHAN) rx_pkt_builer (
+ .rxclk ( rxclk ),
+ .reset ( reset ),
+ .adctime ( adctime ),
+ .chan_rdreq ( chan_rdreq ),
+ .chan_fifodata ( chan_fifodata ),
+ .chan_empty ( chan_empty ),
+ .rd_select ( rd_select ),
+ .chan_usedw ( chan_usedw ),
+ .WR ( WR ),
+ .fifodata ( fifodata ),
+ .have_space ( have_space ) );
+
+ // Detect overrun
+ always @(posedge rxclk)
+ if(reset)
+ rx_overrun <= 1'b0;
+ else if(rx_full[0])
+ rx_overrun <= 1'b1;
+ else if(clear_status)
+ rx_overrun <= 1'b0;
+
+ reg [15:0] test;
+ always @(posedge rxclk)
+ if (reset)
+ test <= 0;
+ else if (~rx_full[0])
+ test <= test + 1;
+
+ // TODO write this genericly
+ wire [15:0]ch[NUM_CHAN:0];
+ assign ch[0] = ch_0;
+ assign ch[1] = ch_1;
+
+ generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
+ begin : generate_channel_fifos
+ wire [15:0] dataout;
+ wire [9:0] usedw;
+
+ assign chan_fifodata = (rd_select[i] ? dataout : 16'bZ);
+ assign chan_usedw = (rd_select[i] ? usedw : 10'bZ);
+ assign chan_empty[i] = usedw < 10'd126;
+
+ fifo_2k_1clk rx_chan_fifo (
+ .aclr ( reset ),
+ .clock ( rxclk ),
+ .data ( ch[i] ),
+ .rdreq ( chan_rdreq[i] ),
+ .wrreq ( ~rx_full[i] & rxstrobe ),
+ .empty ( ),
+ .full ( rx_full[i] ),
+ .q ( dataout ),
+ .usedw ( usedw ) );
+ end
+ endgenerate
+
+ assign debugbus = 0;
+endmodule
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