[Commit-gnuradio] r5839 - gnuradio/branches/developers/matt/u2f/control_lib

[matt]

Author: matt
Date: 2007-06-25 20:50:20 -0600 (Mon, 25 Jun 2007)
New Revision: 5839

Modified:
   gnuradio/branches/developers/matt/u2f/control_lib/serdes_rx.v
Log:
most of the rx process done


Modified: gnuradio/branches/developers/matt/u2f/control_lib/serdes_rx.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/serdes_rx.v       
2007-06-26 02:48:51 UTC (rev 5838)
+++ gnuradio/branches/developers/matt/u2f/control_lib/serdes_rx.v       
2007-06-26 02:50:20 UTC (rev 5839)
@@ -38,19 +38,19 @@
    input fifo_full_i
    );
 
-   localparam COMMA = 8'b101_11100;  // K28.5
-   //localparam IDLE = 8'b001_11100;  // K28.1
-   localparam PKT_START = 8'b110_11100; // K28.6
-   localparam PKT_END = 8'b100_11100;  // K28.4
-   localparam LOS = 8'b111_11111;  // K31.7
-   localparam ERROR = 8'b000_00000; // K0.0
+   localparam K_COMMA = 8'b101_11100;     // 0xBC K28.5
+   localparam K_IDLE = 8'b001_11100;      // 0x3C K28.1
+   localparam K_PKT_START = 8'b110_11100; // 0xDC K28.6
+   localparam K_PKT_END = 8'b100_11100;   // 0x9C K28.4
+   localparam K_LOS = 8'b111_11111;       // 0xFF K31.7
+   localparam K_ERROR = 8'b000_00000;     // 0x00 K00.0
    
    localparam IDLE = 3'd0;
-   localparam START = 3'd1;
-   localparam EVEN = 3'd2;
-   localparam ODD = 3'd3;
-   localparam CRC_EVEN = 3'd4;
-   localparam CRC_ODD = 3'd5;
+   localparam EVEN = 3'd1;
+   localparam ODD = 3'd2;
+   localparam CRC_EVEN = 3'd3;
+   localparam CRC_ODD = 3'd4;
+   localparam ERROR = 3'd5;
    
    reg [17:0] rxd_d1;
    reg [31:0] line_serclk, line_serclk_d1, line_sysclk;
@@ -67,7 +67,11 @@
        rxd_d1 <= 0;
      else
        rxd_d1 <= {ser_rkmsb,ser_rklsb,ser_r};
-   
+
+   always @(posedge ser_rx_clk)
+     if(phase == 1)
+       line_serclk = {rxd_d1[15:0], halfline};
+              
    always @(posedge ser_rx_clk or posedge rst)
      if(rst)
        begin
@@ -81,9 +85,9 @@
           begin
              data_valid <= 0;
              phase <= 0;
-             if(rxd_d1 == {2'b11,PKT_START,PKT_START})
+             if(rxd_d1 == {2'b11,K_PKT_START,K_PKT_START})
                state <= EVEN;
-             else if((rxd_d1[17:16]==2'b01) && (rxd_d1[7:0]==PKT_START))
+             else if((rxd_d1[17:16]==2'b01) && (rxd_d1[7:0]==K_PKT_START))
                begin
                   state <= ODD;
                   holder <= rxd_d1[15:8];
@@ -98,7 +102,7 @@
                   halfline <= rxd_d1[15:0];
                end
             2'b11 :
-              if((rxd_d1[15:0] == {PKT_END,PKT_END}) & phase)
+              if((rxd_d1[15:0] == {K_PKT_END,K_PKT_END}) & ~phase)
                 begin
                    state <= CRC_EVEN;
                    data_valid <= 0;
@@ -129,11 +133,16 @@
           else
             state <= ERROR;
         CRC_EVEN :
-          state <= IDLE;
+          if(rxd_d1[15:0] == CRC)
+            state <= DONE;
+          else
+            state <= ERROR;
         CRC_ODD :
           state <= IDLE;
         ERROR :
           state <= IDLE;
+        DONE :
+          state <= IDLE;
        endcase // case(state)
 
    reg [15:0] CRC;
@@ -149,6 +158,9 @@
 
    CRC16_D16 crc_blk(halfline,CRC,nextCRC);
    assign      crc_pass = ~|nextCRC;
+
+   assign      fifo_error_o = (state == ERROR);
+   assign      fifo_done_o = (state == DONE);
    
 endmodule // serdes_rx