[Commit-gnuradio] r5865 - gnuradio/branches/developers/matt/u2f/control_lib

[matt]

Author: matt
Date: 2007-06-28 01:03:22 -0600 (Thu, 28 Jun 2007)
New Revision: 5865

Modified:
   gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
Log:
compilation fixes


Modified: gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v     
2007-06-28 07:01:24 UTC (rev 5864)
+++ gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v     
2007-06-28 07:03:22 UTC (rev 5865)
@@ -18,7 +18,7 @@
    input wb_stb_i,
    input [15:0] wb_adr_i,
    input [31:0] wb_dat_i,   
-   output reg [31:0] wb_dat_o,
+   output [31:0] wb_dat_o,
    output reg wb_ack_o,
    output wb_err_o,
    output wb_rty_o,
@@ -27,6 +27,7 @@
    input stream_rst,
 
    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+   output [15:0] status,
    
    // Write Interfaces
    input [31:0] wr0_dat_i, input wr0_write_i, input wr0_done_i, input 
wr0_error_i, output wr0_ready_o, output wr0_full_o,
@@ -41,9 +42,10 @@
    output [31:0] rd3_dat_o, input rd3_read_i, input rd3_done_i, input 
rd3_error_i, output rd3_ready_o, output rd3_empty_o
    );
 
-   wire [7:0] sel_a;
+   wire [7:0]   sel_a;
+   //wire       sel_a[0:7];
 
-   wire [2:0]  which_buf = wb_adr_i[13:11];   // address 15:14 selects the 
buffer pool
+   wire [2:0]   which_buf = wb_adr_i[13:11];   // address 15:14 selects the 
buffer pool
    wire [8:0]  buf_addra = wb_adr_i[10:2];     // ignore address 1:0, 32-bit 
access only
  
    decoder_3_8 dec(.sel(which_buf),.res(sel_a));
@@ -59,9 +61,12 @@
    wire [1:0]  write_port[0:7];
    wire [2:0]  dummy[0:7];
    wire        clear [0:7];       
-   wire        done[0:7];
-   wire        error[0:7];
 
+   // wire        done[0:7];
+   // wire        error[0:7];
+   wire [7:0]       done;
+   wire [7:0]      error;
+
    wire        changed [0:7];
 
    wire [31:0] buf_doa[0:7];
@@ -86,7 +91,7 @@
    wire        rd_ready_o[0:7];
    wire        rd_empty_o[0:7];
    
-   wire [15:0] status = {error[7:0],done[7:0]};
+   assign      status = {error[7:0],done[7:0]};
    
    generate
       for(i=0;i<8;i=i+1)
@@ -145,8 +150,7 @@
    endgenerate
    
    // Wishbone Outputs
-   always @*
-     wb_dat_o <= buf_doa[which_buf];
+   assign wb_dat_o = buf_doa[which_buf];
 
    //always @(posedge wb_clk_i)
    //  if(wb_stb_i)