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[Commit-gnuradio] r5923 - gnuradio/branches/developers/matt/u2f/sdr_lib
From: |
matt |
Subject: |
[Commit-gnuradio] r5923 - gnuradio/branches/developers/matt/u2f/sdr_lib |
Date: |
Thu, 5 Jul 2007 22:18:32 -0600 (MDT) |
Author: matt
Date: 2007-07-05 22:18:32 -0600 (Thu, 05 Jul 2007)
New Revision: 5923
Modified:
gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_tx.v
Log:
basic functionality is there
Modified: gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_tx.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_tx.v 2007-07-06
04:16:07 UTC (rev 5922)
+++ gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_tx.v 2007-07-06
04:18:32 UTC (rev 5923)
@@ -1,4 +1,6 @@
+`define DSP_CORE_TX_BASE 128
+
module dsp_core_tx
(input clk, input rst,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
@@ -21,39 +23,40 @@
reg [31:0] phase;
wire [7:0] interp_rate;
wire stb_interp;
+ wire run_tx;
- //setting_reg #(.my_addr(0))
- // (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
- // .in(set_data),.out({i,q}),.changed());
-
- setting_reg #(.my_addr(1)) sr_0
+ setting_reg #(.my_addr(`DSP_CORE_TX_BASE+0)) sr_0
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(phase_inc),.changed());
- setting_reg #(.my_addr(2)) sr_1
+ setting_reg #(.my_addr(`DSP_CORE_TX_BASE+1)) sr_1
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out({scale_i,scale_q}),.changed());
- setting_reg #(.my_addr(3)) sr_2
+ setting_reg #(.my_addr(`DSP_CORE_TX_BASE+2)) sr_2
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(interp_rate),.changed());
+ setting_reg #(.my_addr(`DSP_CORE_TX_BASE+3)) sr_3
+ (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(run_tx),.changed());
+
wire full, empty;
assign tx_done_o = 0;
assign tx_read_o = tx_ready_i & ~full;
assign underrun = empty & stb_interp;
shortfifo txshortfifo
- (.clk(clk),.rst(rst),.datain(tx_dat_i),.dataout({i,q}),
+ (.clk(clk),.rst(rst),.datain(tx_dat_i),.dataout({q,i}),
.read(stb_interp & ~empty),.write(tx_read_o),.full(full),.empty(empty));
- strobe_gen
strobe_gen(.clock(clk),.reset(rst),.enable(1'b1),.rate(interp_rate),
+ strobe_gen
strobe_gen(.clock(clk),.reset(rst),.enable(run_tx),.rate(interp_rate),
.strobe_in(1),.strobe(stb_interp) );
always @(posedge clk)
if(rst)
phase <= 0;
- else
+ else if(run_tx)
phase <= phase + phase_inc;
wire signed [15:0] da, db;
@@ -64,12 +67,12 @@
wire [15:0] i_interp, q_interp;
cic_interp #(.bw(16),.N(4),.log2_of_max_rate(7))
- cic_interp_i(.clock(clk),.reset(rst),.enable(1),.rate(interp_rate),
+ cic_interp_i(.clock(clk),.reset(rst),.enable(run_tx),.rate(interp_rate),
.strobe_in(stb_interp),.strobe_out(1),
.signal_in(i),.signal_out(i_interp));
cic_interp #(.bw(16),.N(4),.log2_of_max_rate(7))
- cic_interp_q(.clock(clk),.reset(rst),.enable(1),.rate(interp_rate),
+ cic_interp_q(.clock(clk),.reset(rst),.enable(run_tx),.rate(interp_rate),
.strobe_in(stb_interp),.strobe_out(1),
.signal_in(q),.signal_out(q_interp));
@@ -83,7 +86,7 @@
.A({{2{da[15]}},da} ), // 18-bit multiplier input
.B({{2{scale_i[15]}},scale_i}), // 18-bit multiplier input
.C(clk), // Clock input
- .CE(1'b1), // Clock enable input
+ .CE(1), // Clock enable input
.R(rst) // Synchronous reset input
);
@@ -92,7 +95,7 @@
.A({{2{db[15]}},da} ), // 18-bit multiplier input
.B({{2{scale_q[15]}},scale_q}), // 18-bit multiplier input
.C(clk), // Clock input
- .CE(1'b1), // Clock enable input
+ .CE(1), // Clock enable input
.R(rst) // Synchronous reset input
);
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