[Commit-gnuradio] r5999 - gnuradio/branches/developers/matt/u2f/control_lib

[matt]

Author: matt
Date: 2007-07-17 11:46:34 -0600 (Tue, 17 Jul 2007)
New Revision: 5999

Added:
   gnuradio/branches/developers/matt/u2f/control_lib/wb_readback_mux.v
Log:
easy way to read back buffer status.  probably not permanent


Added: gnuradio/branches/developers/matt/u2f/control_lib/wb_readback_mux.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/wb_readback_mux.v         
                (rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/wb_readback_mux.v 
2007-07-17 17:46:34 UTC (rev 5999)
@@ -0,0 +1,76 @@
+
+
+// Note -- clocks must be synchronous (derived from the same source)
+// Assumes alt_clk is running at a multiple of wb_clk
+
+module wb_readback_mux
+  (input wb_clk_i,
+   input wb_rst_i,
+   input wb_stb_i,
+   input [15:0] wb_adr_i,
+   output reg [31:0] wb_dat_o,
+   output wb_ack_o,
+   
+   input [31:0] word00,
+   input [31:0] word01,
+   input [31:0] word02,
+   input [31:0] word03,
+   input [31:0] word04,
+   input [31:0] word05,
+   input [31:0] word06,
+   input [31:0] word07,
+   input [31:0] word08,
+   input [31:0] word09,
+   input [31:0] word10,
+   input [31:0] word11,
+   input [31:0] word12,
+   input [31:0] word13,
+   input [31:0] word14,
+   input [31:0] word15
+   );
+
+   reg [15:0]   addr_reg;
+   reg [31:0]   dat_reg;
+   reg                  stb_reg, stb_reg1, stb_reg2;
+   
+   always @(posedge wb_clk_i)
+     if(wb_rst_i)
+       begin
+         addr_reg <= 0;
+         stb_reg <= 0;
+         stb_reg1 <= 0;
+         stb_reg2 <= 0;
+       end
+     else
+       begin
+         addr_reg <= wb_adr_i;
+         stb_reg <= wb_stb_i;
+         stb_reg1 <= stb_reg;
+         stb_reg2 <= stb_reg1;
+       end
+   
+   assign wb_ack_o = stb_reg1 & ~stb_reg2;
+
+   always @(posedge wb_clk_i)
+     case(addr_reg[5:2])
+       0 : wb_dat_o <= word00;
+       1 : wb_dat_o <= word01;
+       2 : wb_dat_o <= word02;
+       3 : wb_dat_o <= word03;
+       4 : wb_dat_o <= word04;
+       5 : wb_dat_o <= word05;
+       6 : wb_dat_o <= word06;
+       7 : wb_dat_o <= word07;
+       8 : wb_dat_o <= word08;
+       9 : wb_dat_o <= word09;
+       10: wb_dat_o <= word10;
+       11: wb_dat_o <= word11;
+       12: wb_dat_o <= word12;
+       13: wb_dat_o <= word13;
+       14: wb_dat_o <= word14;
+       15: wb_dat_o <= word15;
+     endcase // case(addr_reg[3:0])
+      
+endmodule // wb_readback_mux
+
+