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[Commit-gnuradio] r6046 - in gnuradio/branches/developers/jcorgan/radar/
|
From: |
jcorgan |
|
Subject: |
[Commit-gnuradio] r6046 - in gnuradio/branches/developers/jcorgan/radar/gr-radar-mono: doc src/fpga/lib src/fpga/tb src/fpga/top |
|
Date: |
Sat, 21 Jul 2007 14:31:10 -0600 (MDT) |
Author: jcorgan
Date: 2007-07-21 14:31:09 -0600 (Sat, 21 Jul 2007)
New Revision: 6046
Modified:
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/doc/registers.ods
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar.v
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar_config.vh
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar_control.v
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar_rx.v
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/tb/radar_tb.v
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v
Log:
Work in progress. Updated FPGA code only to use side A or side B (Python
support not yet implemented); clean ups.
Modified:
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/doc/registers.ods
===================================================================
(Binary files differ)
Modified:
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar.v
===================================================================
---
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar.v
2007-07-21 18:06:45 UTC (rev 6045)
+++
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar.v
2007-07-21 20:31:09 UTC (rev 6046)
@@ -22,8 +22,8 @@
`include "../lib/radar_config.vh"
module radar(clk_i,saddr_i,sdata_i,s_strobe_i,
- tx_strobe_o,tx_dac_i_o,tx_dac_q_o,
- rx_strobe_i,rx_adc_i_i,rx_adc_q_i,
+ tx_side_o,tx_strobe_o,tx_dac_i_o,tx_dac_q_o,
+ rx_side_o,rx_adc_i_i,rx_adc_q_i,
rx_strobe_o,rx_ech_i_o,rx_ech_q_o);
// System interface
@@ -33,12 +33,13 @@
input s_strobe_i; // Configuration bus write
// Transmit subsystem
+ output tx_side_o; // Transmitter slot
output tx_strobe_o; // Generate an transmitter output sample
output [13:0] tx_dac_i_o; // I channel transmitter output to DAC
output [13:0] tx_dac_q_o; // Q channel transmitter output to DAC
-
+
// Receive subsystem
- input rx_strobe_i; // Indicates receive sample ready from ADC
+ output rx_side_o; // Receiver slot
input [15:0] rx_adc_i_i; // I channel input from ADC
input [15:0] rx_adc_q_i; // Q channel input from ADC
output rx_strobe_o; // Indicates output samples ready for Rx FIFO
@@ -47,6 +48,8 @@
// Application control
wire reset; // Master application reset
+ wire tx_side; // Transmitter slot
+ wire rx_side; // Receiver slot
wire tx_enable; // Transmitter enable
wire rx_enable; // Receiver enable
wire tx_ctrl; // Transmitter on control
@@ -59,7 +62,8 @@
radar_control controller
(.clk_i(clk_i),.saddr_i(saddr_i),.sdata_i(sdata_i),.s_strobe_i(s_strobe_i),
-
.reset_o(reset),.tx_strobe_o(tx_strobe_o),.tx_ctrl_o(tx_ctrl),.rx_ctrl_o(rx_ctrl),
+ .reset_o(reset),.tx_side_o(tx_side_o),.rx_side_o(rx_side_o),
+ .tx_strobe_o(tx_strobe_o),.tx_ctrl_o(tx_ctrl),.rx_ctrl_o(rx_ctrl),
.ampl_o(ampl),.fstart_o(fstart),.fincr_o(fincr));
radar_tx transmitter
@@ -68,8 +72,8 @@
.tx_i_o(tx_dac_i_o),.tx_q_o(tx_dac_q_o) );
radar_rx receiver
- ( .clk_i(clk_i),.rst_i(reset),.ena_i(rx_ctrl & 1'b0), // Disable receiver
for now
- .strobe_i(rx_strobe_i),.rx_in_i_i(rx_adc_i_i),.rx_in_q_i(rx_adc_q_i),
+ ( .clk_i(clk_i),.rst_i(reset),.ena_i(rx_ctrl),
+ .rx_in_i_i(rx_adc_i_i),.rx_in_q_i(rx_adc_q_i),
.rx_strobe_o(rx_strobe_o),.rx_i_o(rx_ech_i_o),.rx_q_o(rx_ech_q_o) );
endmodule // radar
Modified:
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar_config.vh
===================================================================
---
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar_config.vh
2007-07-21 18:06:45 UTC (rev 6045)
+++
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar_config.vh
2007-07-21 20:31:09 UTC (rev 6046)
@@ -23,7 +23,13 @@
`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
`define FR_RADAR_MODE `FR_USER_0
-`define bmFR_RADAR_MODE_RESET 32'h0001
+`define bmFR_RADAR_MODE_RESET 32'b1 << 0
+`define bmFR_RADAR_TXSIDE 32'b1 << 1
+`define bmFR_RADAR_RXSIDE 32'b1 << 2
+`define bmFR_RADAR_LOOP 32'b1 << 3
+`define bmFR_RADAR_META 32'b1 << 4
+`define bmFR_RADAR_DERAMP 32'b1 << 5
+`define bmFR_RADAR_CHIRPS 32'b11 << 6
`define FR_RADAR_TON `FR_USER_1
`define FR_RADAR_TSW `FR_USER_2
@@ -32,4 +38,3 @@
`define FR_RADAR_AMPL `FR_USER_5
`define FR_RADAR_FSTART `FR_USER_6
`define FR_RADAR_FINCR `FR_USER_7
-
Modified:
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar_control.v
===================================================================
---
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar_control.v
2007-07-21 18:06:45 UTC (rev 6045)
+++
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar_control.v
2007-07-21 20:31:09 UTC (rev 6046)
@@ -22,7 +22,8 @@
`include "../lib/radar_config.vh"
module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,
- reset_o,tx_strobe_o,tx_ctrl_o,rx_ctrl_o,
+ reset_o,tx_side_o,rx_side_o,
+ tx_strobe_o,tx_ctrl_o,rx_ctrl_o,
ampl_o,fstart_o,fincr_o);
// System interface
@@ -33,6 +34,8 @@
// Control and configuration outputs
output reset_o;
+ output tx_side_o;
+ output rx_side_o;
output tx_strobe_o;
output tx_ctrl_o;
output rx_ctrl_o;
@@ -42,8 +45,8 @@
// Internal configuration
wire lp_ena;
+ wire md_ena;
wire dr_ena;
- wire md_ena;
wire [1:0] chirps;
wire [15:0] t_on;
wire [15:0] t_sw;
@@ -51,8 +54,16 @@
wire [31:0] t_idle;
// Configuration from host
+ wire [31:0] mode;
setting_reg #(`FR_RADAR_MODE)
sr_mode(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
-
.out({chirps,md_ena,dr_ena,lp_ena,reset_o}));
+ .out(mode));
+ assign reset_o = mode[0];
+ assign tx_side_o = mode[1];
+ assign rx_side_o = mode[2];
+ assign lp_ena = mode[3];
+ assign md_ena = mode[4];
+ assign dr_ena = mode[5];
+ assign chirps = mode[7:6];
setting_reg #(`FR_RADAR_TON)
sr_ton(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out(t_on));
Modified:
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar_rx.v
===================================================================
---
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar_rx.v
2007-07-21 18:06:45 UTC (rev 6045)
+++
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar_rx.v
2007-07-21 20:31:09 UTC (rev 6046)
@@ -22,18 +22,14 @@
`include "../../../../usrp/firmware/include/fpga_regs_common.v"
`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
-module radar_rx(clk_i,rst_i,ena_i,strobe_i,saddr_i,sdata_i,s_strobe_i,
- rx_in_i_i,rx_in_q_i,rx_i_o,rx_q_o,rx_strobe_o);
+module radar_rx(clk_i,rst_i,ena_i,
+ rx_in_i_i,rx_in_q_i,
+ rx_i_o,rx_q_o,rx_strobe_o);
input clk_i;
input rst_i;
input ena_i;
- input strobe_i;
- input [6:0] saddr_i;
- input [31:0] sdata_i;
- input s_strobe_i;
-
input [15:0] rx_in_i_i;
input [15:0] rx_in_q_i;
@@ -41,24 +37,9 @@
output [15:0] rx_q_o;
output rx_strobe_o;
- // Just count up for debugging
- reg [31:0] counter;
+ // Temporary
+ assign rx_strobe_o = ena_i;
+ assign rx_i_o = rx_in_i_i;
+ assign rx_q_o = rx_in_q_i;
- always @(posedge clk_i)
- begin
- if (rst_i | ~ena_i)
- counter <= 32'b0;
- else if (strobe_i & rx_strobe_o)
- counter <= counter + 32'b1;
- end
-
- assign rx_i_o = ena_i ? counter[31:16] : 16'b0;
- assign rx_q_o = ena_i ? counter[15:0] : 16'b0;
-
- // Temporarily we duplicate what master_control.v did to generate
decim_strobe
- // so we can do receive debugging. Later we'll drive rx_strobe_o in bursts
to
- // load receiver data into the rx fifo.
- strobe_gen rx_strobe_gen
- (
.clock(clk_i),.reset(rst_i),.enable(ena_i),.rate(7),.strobe_in(strobe_i),.strobe(rx_strobe_o)
);
-
endmodule // radar_rx
Modified:
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/tb/radar_tb.v
===================================================================
---
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/tb/radar_tb.v
2007-07-21 18:06:45 UTC (rev 6045)
+++
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/tb/radar_tb.v
2007-07-21 20:31:09 UTC (rev 6046)
@@ -41,7 +41,6 @@
wire [13:0] tx_dac_q;
// ADC bus
- reg rx_strobe;
reg [15:0] rx_adc_i;
reg [15:0] rx_adc_q;
@@ -56,7 +55,7 @@
radar uut
(.clk_i(clk),.saddr_i(saddr),.sdata_i(sdata),.s_strobe_i(s_strobe),
.tx_strobe_o(tx_strobe),.tx_dac_i_o(tx_dac_i),.tx_dac_q_o(tx_dac_q),
- .rx_strobe_i(rx_strobe),.rx_adc_i_i(rx_adc_i),.rx_adc_q_i(rx_adc_q),
+ .rx_adc_i_i(rx_adc_i),.rx_adc_q_i(rx_adc_q),
.rx_strobe_o(fifo_strobe),.rx_ech_i_o(fifo_i),.rx_ech_q_o(fifo_q));
// Start up initialization
@@ -68,7 +67,6 @@
saddr = 0;
sdata = 0;
s_strobe = 0;
- rx_strobe = 1;
rx_adc_i = 0;
rx_adc_q = 0;
mode = 0;
@@ -187,8 +185,8 @@
#20 set_ton(320-1); // 5us on time
#20 set_tsw(26-1); // 406ns switching time
- #20 set_tlook(320-1); // 5us look time
- #20 set_tidle(3174-1); // 60us pulse period
+ #20 set_tlook(640-1); // 10us look time
+ #20 set_tidle(2854-1); // 60us pulse period
#20 set_ampl(16'd9946);
#20 set_fstart(32'h80000000); // -16 to 16 MHz
Modified:
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf
===================================================================
(Binary files differ)
Modified:
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf
===================================================================
---
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf
2007-07-21 18:06:45 UTC (rev 6045)
+++
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf
2007-07-21 20:31:09 UTC (rev 6046)
@@ -1,8 +1,5 @@
{ "Warning" "WSGN_SEARCH_FILE"
"../../../../../trunk/usrp/fpga/megacells/bustri.v 1 1 " "Warning: Using design
file ../../../../../trunk/usrp/fpga/megacells/bustri.v, which is not specified
as a design file for the current project, but contains definitions for 1 design
units and 1 entities in project" { } { } 0 0 "Using design file %1!s!, which
is not specified as a design file for the current project, but contains
definitions for %2!d! design units and %3!d! entities in project" 1 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE"
"../../../../../trunk/usrp/fpga/megacells/fifo_4k.v 10 10 " "Warning: Using
design file ../../../../../trunk/usrp/fpga/megacells/fifo_4k.v, which is not
specified as a design file for the current project, but contains definitions
for 10 design units and 10 entities in project" { } { } 0 0 "Using design
file %1!s!, which is not specified as a design file for the current project,
but contains definitions for %2!d! design units and %3!d! entities in project"
1 0 "" 0}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "write_done
serial_io.v(48) " "Warning (10036): Verilog HDL or VHDL warning at
serial_io.v(48): object \"write_done\" assigned a value but never read" { } {
{ "../../../../usrp/fpga/sdr_lib/serial_io.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/serial_io.v" 48 0 0 } } } 0 10036
"Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but
never read" 1 0 "" 0}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 atr_delay.v(58)
" "Warning (10230): Verilog HDL assignment warning at atr_delay.v(58):
truncated value with size 32 to match size of target (12)" { } { {
"../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/atr_delay.v" 58 0 0 } } } 0 10230
"Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to
match size of target (%2!d!)" 1 0 "" 0}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 atr_delay.v(71)
" "Warning (10230): Verilog HDL assignment warning at atr_delay.v(71):
truncated value with size 32 to match size of target (12)" { } { {
"../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/atr_delay.v" 71 0 0 } } } 0 10230
"Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to
match size of target (%2!d!)" 1 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rx_delay 12 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_rx_delay\" is
connected to a signal of width 12. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rx_delay" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 138 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_tx_delay 12 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_tx_delay\" is
connected to a signal of width 12. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_tx_delay" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 137 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rxval_3 16 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_atr_rxval_3\" is
connected to a signal of width 16. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rxval_3" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 134 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
@@ -29,7 +26,6 @@
{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_decim 8 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_decim\" is connected to a
signal of width 8. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_decim" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 51 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_interp 8 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_interp\" is connected to a
signal of width 8. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_interp" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 50 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_mstr_ctrl 8 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_mstr_ctrl\" is
connected to a signal of width 8. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/master_control.v" "sr_mstr_ctrl" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 42 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "rate rx_strobe_gen 32
8 " "Warning: Port \"rate\" on the entity instantiation of \"rx_strobe_gen\" is
connected to a signal of width 32. The formal width of the signal in the module
is 8. Extra bits will be ignored." { } { { "../lib/radar_rx.v"
"rx_strobe_gen" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_rx.v" 62 0 0 } } } 0 0
"Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be ignored." 1 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage11 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage11\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage11" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 100 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage10 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage10\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage10" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 99 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage9 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage9\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage9" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 98 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
@@ -42,99 +38,20 @@
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage2 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage2\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage2" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 91 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage1 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage1\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage1" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 90 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6
cordic_stage0 16 15 " "Warning: Port \"ordered port 6\" on the entity
instantiation of \"cordic_stage0\" is connected to a signal of width 16. The
formal width of the signal in the module is 15. Extra bits will be ignored." {
} { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage0" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 89 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be ignored." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ampl 16 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_ampl\" is connected to a
signal of width 16. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_ampl" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 59 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_mode 8 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_mode\" is connected to a
signal of width 8. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_mode" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 56 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Warning: The following nets
are missing source, defaulting to GND" { } { } 0 0 "The following nets are
missing source, defaulting to GND" 1 0 "" 0}
-{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Warning: The following nets
are missing source, defaulting to GND" { { "Warning"
"WSGN_TRI_BUS_MISSING_SOURCE_SUB"
"radar:radar_mono\|radar_control:controller\|rst_i " "Warning: Net
\"radar:radar_mono\|radar_control:controller\|rst_i\"" { } { {
"../lib/radar_control.v" "rst_i" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 55 -1 0 } } } 0
0 "Net \"%1!s!\"" 1 0 "" 0} } { } 0 0 "The following nets are missing source,
defaulting to GND" 0 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ampl 16 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_ampl\" is connected to a
signal of width 16. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_ampl" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 81 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tlook 16 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_tlook\" is connected to a
signal of width 16. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_tlook" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 75 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tsw 16 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_tsw\" is connected to a signal
of width 16. The formal width of the signal in the module is 32. Extra bits
will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_tsw" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 72 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ton 16 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_ton\" is connected to a signal
of width 16. The formal width of the signal in the module is 32. Extra bits
will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_ton" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 69 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_rxformat 11 32 "
"Warning: Port \"out\" on the entity instantiation of \"sr_rxformat\" is
connected to a signal of width 11. The formal width of the signal in the module
is 32. Extra bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/rx_buffer.v" "sr_rxformat" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/rx_buffer.v" 66 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_rxmux 20 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_rxmux\" is connected to a
signal of width 20. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/adc_interface.v" "sr_rxmux" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/adc_interface.v" 54 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_dco_en 4 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_dco_en\" is connected to a
signal of width 4. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../../../../usrp/fpga/sdr_lib/adc_interface.v" "sr_dco_en" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/adc_interface.v" 32 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[0\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[0\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[1\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[1\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[2\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[2\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[3\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[3\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[4\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[4\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[5\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[5\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[6\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[6\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[7\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[7\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[8\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[8\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[9\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[9\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[10\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[10\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[11\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[11\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[12\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[12\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[13\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[13\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[14\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[14\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[15\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[15\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[16\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[16\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[17\]
data_in GND " "Warning: Reduced register
\"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[17\]\"
with stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"master_control:master_control\|atr_delay:atr_delay\|state.0001 data_in GND "
"Warning: Reduced register
\"master_control:master_control\|atr_delay:atr_delay\|state.0001\" with stuck
data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text
"H:/gnuradio/radar/usrp/fpga/sdr_lib/atr_delay.v" 31 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "MYSTERY_SIGNAL GND " "Warning: Pin
\"MYSTERY_SIGNAL\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 24 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "FX2_3 GND " "Warning: Pin \"FX2_3\"
stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 33 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[0\] GND " "Warning: Pin
\"tx_b\[0\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[1\] GND " "Warning: Pin
\"tx_b\[1\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[2\] GND " "Warning: Pin
\"tx_b\[2\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[3\] GND " "Warning: Pin
\"tx_b\[3\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[4\] GND " "Warning: Pin
\"tx_b\[4\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[5\] GND " "Warning: Pin
\"tx_b\[5\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[6\] GND " "Warning: Pin
\"tx_b\[6\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[7\] GND " "Warning: Pin
\"tx_b\[7\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[8\] GND " "Warning: Pin
\"tx_b\[8\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[9\] GND " "Warning: Pin
\"tx_b\[9\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[10\] GND " "Warning: Pin
\"tx_b\[10\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[11\] GND " "Warning: Pin
\"tx_b\[11\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[12\] GND " "Warning: Pin
\"tx_b\[12\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[13\] GND " "Warning: Pin
\"tx_b\[13\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "TXSYNC_B GND " "Warning: Pin
\"TXSYNC_B\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 44 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC
or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "usbrdy\[0\] GND " "Warning: Pin
\"usbrdy\[0\]\" stuck at GND" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 49 -1 0 } } }
0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0} } { } 0 0 "Output pins are stuck
at VCC or GND" 0 0 "" 0}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[0\] " "Warning: No output dependent
on input pin \"rx_b_a\[0\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[1\] " "Warning: No output dependent
on input pin \"rx_b_a\[1\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[2\] " "Warning: No output dependent
on input pin \"rx_b_a\[2\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[3\] " "Warning: No output dependent
on input pin \"rx_b_a\[3\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[4\] " "Warning: No output dependent
on input pin \"rx_b_a\[4\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[5\] " "Warning: No output dependent
on input pin \"rx_b_a\[5\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[6\] " "Warning: No output dependent
on input pin \"rx_b_a\[6\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[7\] " "Warning: No output dependent
on input pin \"rx_b_a\[7\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[8\] " "Warning: No output dependent
on input pin \"rx_b_a\[8\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[9\] " "Warning: No output dependent
on input pin \"rx_b_a\[9\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[10\] " "Warning: No output dependent
on input pin \"rx_b_a\[10\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[11\] " "Warning: No output dependent
on input pin \"rx_b_a\[11\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[0\] " "Warning: No output dependent
on input pin \"rx_b_b\[0\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[1\] " "Warning: No output dependent
on input pin \"rx_b_b\[1\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[2\] " "Warning: No output dependent
on input pin \"rx_b_b\[2\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[3\] " "Warning: No output dependent
on input pin \"rx_b_b\[3\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[4\] " "Warning: No output dependent
on input pin \"rx_b_b\[4\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[5\] " "Warning: No output dependent
on input pin \"rx_b_b\[5\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[6\] " "Warning: No output dependent
on input pin \"rx_b_b\[6\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[7\] " "Warning: No output dependent
on input pin \"rx_b_b\[7\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[8\] " "Warning: No output dependent
on input pin \"rx_b_b\[8\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[9\] " "Warning: No output dependent
on input pin \"rx_b_b\[9\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[10\] " "Warning: No output dependent
on input pin \"rx_b_b\[10\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[11\] " "Warning: No output dependent
on input pin \"rx_b_b\[11\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "MYSTERY_SIGNAL GND " "Info:
Pin MYSTERY_SIGNAL has GND driving its datain port" { } { {
"usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 24 -1 0 } } {
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "MYSTERY_SIGNAL" }
} } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MYSTERY_SIGNAL
} "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" ""
{ Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
MYSTERY_SIGNAL } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain
port" 1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC
driving datain port -- changes to this connectivity may change fitting results"
0 0 "" 0}
-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FX2_3 GND " "Info: Pin FX2_3
has GND driving its datain port" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 33 -1 0 } } {
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FX2_3" } } } } {
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { FX2_3 }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
FX2_3 } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1
0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[0\] GND " "Info: Pin
tx_b\[0\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[0\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[0] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[1\] GND " "Info: Pin
tx_b\[1\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[1\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[1] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[2\] GND " "Info: Pin
tx_b\[2\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[2\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[2] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[3\] GND " "Info: Pin
tx_b\[3\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[3\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[3] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[4\] GND " "Info: Pin
tx_b\[4\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[4\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[4] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[5\] GND " "Info: Pin
tx_b\[5\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[5\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[5] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[6\] GND " "Info: Pin
tx_b\[6\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[6\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[6] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[7\] GND " "Info: Pin
tx_b\[7\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[7\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[7] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[8\] GND " "Info: Pin
tx_b\[8\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[8\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[8] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[9\] GND " "Info: Pin
tx_b\[9\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[9\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[9] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[10\] GND " "Info: Pin
tx_b\[10\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[10\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[10] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[11\] GND " "Info: Pin
tx_b\[11\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[11\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[11] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[12\] GND " "Info: Pin
tx_b\[12\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[12\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[12] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[13\] GND " "Info: Pin
tx_b\[13\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[13\]" } } }
} { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[13] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
tx_b[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "TXSYNC_B GND " "Info: Pin
TXSYNC_B has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 44 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "TXSYNC_B" } } } }
{ "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { TXSYNC_B }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
TXSYNC_B } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port"
1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "usbrdy\[0\] GND " "Info: Pin
usbrdy\[0\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 49 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "usbrdy\[0\]" } }
} } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { usbrdy[0] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
usbrdy[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain
port" 1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC
driving datain port -- changes to this connectivity may change fitting results"
0 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ampl 16 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_ampl\" is connected to a
signal of width 16. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_ampl" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 69 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tlook 16 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_tlook\" is connected to a
signal of width 16. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_tlook" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 63 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tsw 16 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_tsw\" is connected to a signal
of width 16. The formal width of the signal in the module is 32. Extra bits
will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_tsw" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 60 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ton 16 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_ton\" is connected to a signal
of width 16. The formal width of the signal in the module is 32. Extra bits
will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_ton" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 57 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_mode 6 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_mode\" is connected to a
signal of width 6. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_mode" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 54 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ampl 16 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_ampl\" is connected to a
signal of width 16. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_ampl" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 70 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tlook 16 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_tlook\" is connected to a
signal of width 16. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_tlook" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 64 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tsw 16 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_tsw\" is connected to a signal
of width 16. The formal width of the signal in the module is 32. Extra bits
will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_tsw" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 61 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ton 16 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_ton\" is connected to a signal
of width 16. The formal width of the signal in the module is 32. Extra bits
will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_ton" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 58 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_mode 6 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_mode\" is connected to a
signal of width 6. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../lib/radar_control.v" "sr_mode" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 55 0 0 } } } 0
0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a
signal of width %3!d!. The formal width of the signal in the module is %4!d!.
Extra bits will be left dangling without any fanout logic." 1 0 "" 0}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design
contains * input pin(s) that do not drive logic" { { "Warning"
"WCUT_CUT_UNNECESSARY_INPUT_PIN" "usbctl\[0\] " "Warning: No output dependent
on input pin \"usbctl\[0\]\"" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 48 -1 0 } } }
0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0} } { } 0 0 "Design
contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "3 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "MYSTERY_SIGNAL GND " "Info:
Pin MYSTERY_SIGNAL has GND driving its datain port" { } { {
"usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 24 -1 0 } } {
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "MYSTERY_SIGNAL" }
} } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MYSTERY_SIGNAL
} "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" ""
{ Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
MYSTERY_SIGNAL } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain
port" 1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC
driving datain port -- changes to this connectivity may change fitting results"
0 0 "" 0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "3 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FX2_3 GND " "Info: Pin FX2_3
has GND driving its datain port" { } { { "usrp_radar_mono.v" "" { Text
"H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 33 -1 0 } } {
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FX2_3" } } } } {
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { FX2_3 }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
FX2_3 } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1
0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving
datain port -- changes to this connectivity may change fitting results" 0 0 ""
0}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "3 " "Warning:
Following * pins have nothing, GND, or VCC driving datain port -- changes to
this connectivity may change fitting results" { { "Info"
"IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "usbrdy\[0\] GND " "Info: Pin
usbrdy\[0\] has GND driving its datain port" { } { { "usrp_radar_mono.v" "" {
Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 49 -1 0 }
} { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment
"c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "usbrdy\[0\]" } }
} } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan
"c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { usbrdy[0] }
"NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" {
Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" {
usbrdy[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain
port" 1 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC
driving datain port -- changes to this connectivity may change fitting results"
0 0 "" 0}
Modified:
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v
===================================================================
---
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v
2007-07-21 18:06:45 UTC (rev 6045)
+++
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v
2007-07-21 20:31:09 UTC (rev 6046)
@@ -95,28 +95,31 @@
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Transmit Side
+ wire tx_side;
wire [13:0] tx_i, tx_q;
wire [13:0] tx_dac;
+ wire tx_sync;
dac_interface dac(.clk_i(clk64),.rst_i(tx_dsp_reset),.ena_i(enable_tx),
.strobe_i(tx_sample_strobe),.tx_i_i(tx_i),.tx_q_i(tx_q),
- .tx_data_o(tx_dac),.tx_sync_o(TXSYNC_A));
+ .tx_data_o(tx_dac),.tx_sync_o(tx_sync));
- assign tx_a = tx_dac;
-
- // Wedge DAC #2 at zero
- assign TXSYNC_B = 1'b0;
- assign tx_b = 14'b0;
+ // Route transmitted signal to side A or side B
+ assign tx_a = tx_side ? 14'b0 : tx_dac;
+ assign tx_b = tx_side ? tx_dac : 14'b0;
+ assign TXSYNC_A = tx_side ? 1'b0 : tx_sync;
+ assign TXSYNC_B = tx_side ? tx_sync : 1'b0;
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Receive Side
- wire rx_sample_strobe, rx_strobe;
+ wire rx_side;
+ wire rx_strobe;
wire [15:0] rx_adc0_i, rx_adc0_q;
wire [15:0] rx_buf_i, rx_buf_q;
adc_interface
adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(enable_rx),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
-
.rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(),.rx_b_b(),
+
.rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b),
.rssi_0(),.rssi_1(),.rssi_2(),.rssi_3(),
.ddc0_in_i(rx_adc0_i),.ddc0_in_q(rx_adc0_q),
.ddc1_in_i(),.ddc1_in_q(),
@@ -140,10 +143,9 @@
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Top level application
-
radar radar_mono (
.clk_i(clk64),.saddr_i(serial_addr),.sdata_i(serial_data),.s_strobe_i(serial_strobe),
- .tx_strobe_o(tx_sample_strobe),.tx_dac_i_o(tx_i),.tx_dac_q_o(tx_q),
-
.rx_strobe_i(rx_sample_strobe),.rx_adc_i_i(rx_adc0_i),.rx_adc_q_i(rx_adc0_q),
+
.tx_side_o(tx_side),.tx_strobe_o(tx_sample_strobe),.tx_dac_i_o(tx_i),.tx_dac_q_o(tx_q),
+ .rx_side_o(rx_side),.rx_adc_i_i(rx_adc0_i),.rx_adc_q_i(rx_adc0_q),
.rx_strobe_o(rx_strobe),.rx_ech_i_o(rx_buf_i),.rx_ech_q_o(rx_buf_q)
);
@@ -172,8 +174,8 @@
.tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
.enable_tx(enable_tx),.enable_rx(enable_rx),
.interp_rate(),.decim_rate(),
- .tx_sample_strobe(),.strobe_interp(), // tx_sample_strobe now generated
by radar transmitter module
- .rx_sample_strobe(rx_sample_strobe),.strobe_decim(),
+ .tx_sample_strobe(),.strobe_interp(),
+ .rx_sample_strobe(),.strobe_decim(),
.tx_empty(tx_empty),
.debug_0(),.debug_1(),
.debug_2(),.debug_3(),
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- [Commit-gnuradio] r6046 - in gnuradio/branches/developers/jcorgan/radar/gr-radar-mono: doc src/fpga/lib src/fpga/tb src/fpga/top,
jcorgan <=