[Commit-gnuradio] r6061 - gnuradio/branches/developers/matt/u2f/control_lib

[matt]

Author: matt
Date: 2007-07-24 16:12:52 -0600 (Tue, 24 Jul 2007)
New Revision: 6061

Modified:
   gnuradio/branches/developers/matt/u2f/control_lib/fifo_int.v
Log:
mostly code clarifications, now listens to rd_done_i


Modified: gnuradio/branches/developers/matt/u2f/control_lib/fifo_int.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/fifo_int.v        
2007-07-24 22:10:44 UTC (rev 6060)
+++ gnuradio/branches/developers/matt/u2f/control_lib/fifo_int.v        
2007-07-24 22:12:52 UTC (rev 6061)
@@ -59,8 +59,6 @@
    wire [2:0] port = ctrl_reg[27:25];  // Ignored in this block
    wire [3:0] buff_num = ctrl_reg[31:28];  // Ignored here ?
    
-   wire       rd_en, wr_en;
-   
    assign     dat_to_buf = wr_dat_i;
    assign     rd_dat_o = dat_from_buf;
    
@@ -109,7 +107,7 @@
                  addr_o <= addr_o + 1;
                  if(rd_error_i)
                    state <= ERROR;
-                 else if(addr_o == lastline + 9'd1)
+                 else if((addr_o == lastline + 9'd1)|rd_done_i)
                    state <= DONE;
               end
           
@@ -132,20 +130,23 @@
           
         endcase // case(state)
    
-   // FIXME read side ignores rd_done_i and step for now
-   
-   assign rd_en = (state == PRE_READ) || ((state == READING) && rd_read_i); // 
unused now
-   assign rd_empty_o = (state != READING) && (state != PRE_READ);
-   assign rd_ready_o = (state == READING);
+   // FIXME ignores step for now
 
-   assign wr_en = (state == WRITING) && wr_write_i;  // unused now IF this is 
a timing problem, we could always enable when in this state
-   assign we_o = (state == WRITING) && wr_write_i;  // IF this is a timing 
problem, we could always write when in this state
-   assign wr_full_o = (state != WRITING);
-   assign wr_ready_o = (state == WRITING);
-
-   //assign    en_o = rd_en | wr_en;
-   assign    en_o = ~((state==READING)& ~rd_read_i);   // test faster signal
+   assign     rd_empty_o = (state != READING); // && (state != PRE_READ);
+   assign     rd_ready_o = (state == READING);
    
-   assign done = (state == DONE);
-   assign error = (state == ERROR);
+   assign     wr_full_o = (state != WRITING);
+   assign     wr_ready_o = (state == WRITING);
+   
+   assign     we_o = (state == WRITING) && wr_write_i;  // FIXME potential 
critical path
+                   // IF this is a timing problem, we could always write when 
in this state
+   assign     en_o = ~((state==READING)& ~rd_read_i);   // FIXME potential 
critical path
+   
+   assign     done = (state == DONE);
+   assign     error = (state == ERROR);
+   
+   //wire       rd_en = (state == PRE_READ) || ((state == READING) && 
rd_read_i);
+   //wire       wr_en = (state == WRITING) && wr_write_i;  // IF this is a 
timing problem, we could always enable when in this state
+   //assign     en_o = rd_en | wr_en;   
+   
 endmodule // fifo_int