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[Commit-gnuradio] r6086 - in gnuradio/branches/developers/jcorgan/radar/
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From: |
jcorgan |
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Subject: |
[Commit-gnuradio] r6086 - in gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga: lib top |
|
Date: |
Mon, 30 Jul 2007 19:42:39 -0600 (MDT) |
Author: jcorgan
Date: 2007-07-30 19:42:39 -0600 (Mon, 30 Jul 2007)
New Revision: 6086
Added:
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/fifo32_4k.v
Modified:
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/Makefile.am
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar_rx.v
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v
Log:
Work in progress, added receiver buffering for debug output.
Modified:
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/Makefile.am
===================================================================
---
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/Makefile.am
2007-07-30 23:24:22 UTC (rev 6085)
+++
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/Makefile.am
2007-07-31 01:42:39 UTC (rev 6086)
@@ -28,6 +28,7 @@
radar_tx.v \
radar_rx.v \
dac_interface.v \
+ fifo32_1k.v \
cordic_nco.v
MOSTLYCLEANFILES = *~
Added:
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/fifo32_4k.v
===================================================================
---
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/fifo32_4k.v
(rev 0)
+++
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/fifo32_4k.v
2007-07-31 01:42:39 UTC (rev 6086)
@@ -0,0 +1,161 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: scfifo
+
+// ============================================================
+// File Name: fifo32_4k.v
+// Megafunction Name(s):
+// scfifo
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 7.1 Build 178 06/25/2007 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2007 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module fifo32_4k (
+ clock,
+ data,
+ rdreq,
+ sclr,
+ wrreq,
+ empty,
+ q);
+
+ input clock;
+ input [31:0] data;
+ input rdreq;
+ input sclr;
+ input wrreq;
+ output empty;
+ output [31:0] q;
+
+ wire sub_wire0;
+ wire [31:0] sub_wire1;
+ wire empty = sub_wire0;
+ wire [31:0] q = sub_wire1[31:0];
+
+ scfifo scfifo_component (
+ .rdreq (rdreq),
+ .sclr (sclr),
+ .clock (clock),
+ .wrreq (wrreq),
+ .data (data),
+ .empty (sub_wire0),
+ .q (sub_wire1)
+ // synopsys translate_off
+ ,
+ .aclr (),
+ .almost_empty (),
+ .almost_full (),
+ .full (),
+ .usedw ()
+ // synopsys translate_on
+ );
+ defparam
+ scfifo_component.add_ram_output_register = "OFF",
+ scfifo_component.intended_device_family = "Cyclone",
+ scfifo_component.lpm_numwords = 4096,
+ scfifo_component.lpm_showahead = "OFF",
+ scfifo_component.lpm_type = "scfifo",
+ scfifo_component.lpm_width = 32,
+ scfifo_component.lpm_widthu = 12,
+ scfifo_component.overflow_checking = "OFF",
+ scfifo_component.underflow_checking = "OFF",
+ scfifo_component.use_eab = "ON";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Depth NUMERIC "4096"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
+// Retrieval info: PRIVATE: UsedW NUMERIC "0"
+// Retrieval info: PRIVATE: Width NUMERIC "32"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "32"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
+// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
+// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
+// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
Modified:
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar_rx.v
===================================================================
---
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar_rx.v
2007-07-30 23:24:22 UTC (rev 6085)
+++
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/lib/radar_rx.v
2007-07-31 01:42:39 UTC (rev 6086)
@@ -35,20 +35,80 @@
output [15:0] rx_i_o;
output [15:0] rx_q_o;
- output rx_strobe_o;
+ output reg rx_strobe_o;
- // Temporary
- assign rx_strobe_o = ena_i;
+ reg [15:0] count;
- reg [31:0] count;
+ // Temporary receiver debugging
+ always @(posedge clk_i)
+ if (rst_i | ~ena_i)
+ count <= 16'b0;
+ else
+ count <= count + 16'b1;
+ wire [31:0] fifo_data = {count[15:0],16'hAA55};
+ // End temporary receiver debugging
+
+ // Need to buffer received samples as they come in at 32 bits per cycle
+ // but the rx_buffer.v fifo is only 16 bits wide.
+ //
+ reg fifo_read;
+ wire [31:0] fifo_out;
+ wire fifo_empty;
+
+ fifo32_4k fifo(.clock(clk_i),.sclr(rst_i),
+ .data(fifo_data),.wrreq(ena_i),
+ .q(fifo_out),.rdreq(fifo_read),
+ .empty(fifo_empty) );
+
+ `define ST_RD_IDLE 4'b0001
+ `define ST_RD_FIFO 4'b0010
+ `define ST_WR_I 4'b0100
+ `define ST_WR_Q 4'b1000
+
+ reg [3:0] state;
+
always @(posedge clk_i)
if (rst_i | ~ena_i)
- count <= 32'b0;
+ begin
+ state <= `ST_RD_IDLE;
+ rx_strobe_o <= 1'b0;
+ fifo_read <= 1'b0;
+ end
else
- count <= count + 32'b1;
+ case (state)
+ `ST_RD_IDLE:
+ if (!fifo_empty)
+ begin
+ state <= `ST_RD_FIFO;
+ fifo_read <= 1'b1;
+ end
- assign rx_i_o = count[15:0];
- assign rx_q_o = 16'hAA55;
+ `ST_RD_FIFO:
+ begin
+ state <= `ST_WR_I;
+ fifo_read <= 1'b0;
+ rx_strobe_o <= 1'b1;
+ end
+ `ST_WR_I:
+ begin
+ state <= `ST_WR_Q;
+ rx_strobe_o <= 1'b0;
+ end
+
+ `ST_WR_Q:
+ if (!fifo_empty)
+ begin
+ state <= `ST_RD_FIFO;
+ fifo_read <= 1'b1;
+ end
+ else
+ state <= `ST_RD_IDLE;
+
+ endcase // case(state)
+
+ assign rx_i_o = fifo_out[31:16];
+ assign rx_q_o = fifo_out[15:0];
+
endmodule // radar_rx
Modified:
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf
===================================================================
---
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf
2007-07-30 23:24:22 UTC (rev 6085)
+++
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf
2007-07-31 01:42:39 UTC (rev 6086)
@@ -29,6 +29,7 @@
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13,
2003"
set_global_assignment -name LAST_QUARTUS_VERSION "7.1 SP1"
+set_global_assignment -name MESSAGE_SUPPRESSION_RULE_FILE usrp_radar_mono.srf
# Pin & Location Assignments
# ==========================
@@ -325,8 +326,8 @@
# Classic Timing Assignments
# ==========================
-set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK
- set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK
+ set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK
+set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK
# end CLOCK(SCLK)
# ---------------
@@ -336,8 +337,8 @@
# Classic Timing Assignments
# ==========================
-set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk
- set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id
master_clk
+ set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk
+set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk
# end CLOCK(master_clk)
# ---------------------
@@ -347,40 +348,39 @@
# Classic Timing Assignments
# ==========================
-set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk
- set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk
+ set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk
+set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk
# end CLOCK(usbclk)
# -----------------
-# ----------------------
+# -----------------------------
# start ENTITY(usrp_radar_mono)
# Classic Timing Assignments
# ==========================
- set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK
- set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk
- set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
+set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK
+set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk
+set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
- set_instance_assignment -name PARTITION_HIERARCHY
no_file_for_top_partition -to | -section_id Top
- set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE
-section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition
-to | -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(usrp_radar_mono)
-# --------------------
-set_global_assignment -name MESSAGE_SUPPRESSION_RULE_FILE usrp_radar_mono.srf
-set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/rx_buffer.v
+# ---------------------------
set_global_assignment -name VERILOG_FILE usrp_radar_mono.v
set_global_assignment -name VERILOG_FILE dacpll.v
set_global_assignment -name VERILOG_FILE ../lib/cordic_nco.v
set_global_assignment -name VERILOG_FILE ../lib/dac_interface.v
+set_global_assignment -name VERILOG_FILE ../lib/fifo32_4k.v
set_global_assignment -name VERILOG_FILE ../lib/radar_control.v
set_global_assignment -name VERILOG_FILE ../lib/radar_rx.v
set_global_assignment -name VERILOG_FILE ../lib/radar_tx.v
@@ -395,6 +395,7 @@
set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/io_pins.v
set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/master_control.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v
+set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/rx_buffer.v
set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/rx_dcoffset.v
set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/serial_io.v
set_global_assignment -name VERILOG_FILE
../../../../usrp/fpga/sdr_lib/setting_reg.v
Modified:
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf
===================================================================
(Binary files differ)
Modified:
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v
===================================================================
---
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v
2007-07-30 23:24:22 UTC (rev 6085)
+++
gnuradio/branches/developers/jcorgan/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v
2007-07-31 01:42:39 UTC (rev 6086)
@@ -153,9 +153,9 @@
wire [31:0] capabilities;
assign capabilities[7] = 0; // `TX_CAP_HB;
- assign capabilities[6:4] = 2; // `TX_CAP_NCHAN;
+ assign capabilities[6:4] = 1; // `TX_CAP_NCHAN;
assign capabilities[3] = 0; // `RX_CAP_HB;
- assign capabilities[2:0] = 2; // `RX_CAP_NCHAN;
+ assign capabilities[2:0] = 1; // `RX_CAP_NCHAN;
serial_io serial_io
( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
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