[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Commit-gnuradio] r6353 - in gnuradio/branches/developers/zhuochen/inban
|
From: |
zhuochen |
|
Subject: |
[Commit-gnuradio] r6353 - in gnuradio/branches/developers/zhuochen/inband/usrp/fpga: inband_lib megacells toplevel/usrp_inband_usb |
|
Date: |
Fri, 7 Sep 2007 13:58:21 -0600 (MDT) |
Author: zhuochen
Date: 2007-09-07 13:58:21 -0600 (Fri, 07 Sep 2007)
New Revision: 6353
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/packet_builder.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/megacells/fifo_2k_1clk.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
Log:
Fixing RX bug, still have megacell problem so we are currently reverted back
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-09-07 17:47:53 UTC (rev 6352)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-09-07 19:58:21 UTC (rev 6353)
@@ -46,7 +46,7 @@
/* State registers */
reg [2:0] reader_state;
-
+ /* Local registers */
reg [6:0] payload_len;
reg [6:0] read_len;
reg [31:0] timestamp;
@@ -87,7 +87,7 @@
rdreq <= 1;
underrun <= 0;
end
- else if (burst == 1)
+ if (burst == 1 && pkt_waiting == 0)
underrun <= 1;
if (tx_strobe == 1)
@@ -183,7 +183,7 @@
end
end
- // Send the samples to the tx_chain
+ // Send the samples to the tx_chain
SEND:
begin
reader_state <= WAITSTROBE;
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/packet_builder.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/packet_builder.v
2007-09-07 17:47:53 UTC (rev 6352)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/packet_builder.v
2007-09-07 19:58:21 UTC (rev 6353)
@@ -46,12 +46,14 @@
reg [3:0] check_next;
wire [8:0] chan_used;
wire [31:0] true_rssi;
+ wire [4:0] true_channel;
- assign debugbus = {state, chan_empty[0], chan_empty[1], check_next[0],
+ assign debugbus = {state, chan_empty[0], underrun[0], check_next[0],
have_space, rd_select[0]};
assign chan_used = chan_usedw[8:0];
assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) :
- ((rd_select[0]) ?
rssi_1:rssi_0);
+ ((rd_select[0]) ?
rssi_1:rssi_0);
+ assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next -
4'd1});
always @(posedge rxclk)
begin
if (reset)
@@ -65,6 +67,7 @@
end
else case (state)
`IDLE: begin
+ chan_rdreq <= #1 0;
if (have_space)
begin
if(~chan_empty[check_next])
@@ -90,14 +93,12 @@
end
`HEADER2: begin
- fifodata[`CHAN] <= #1 (check_next == 4'd0 ? 5'h1f : {1'd0,
check_next - 4'd1});
+ fifodata[`CHAN] <= #1 true_channel;
fifodata[`RSSI] <= #1 true_rssi[5:0];
fifodata[`BURST] <= #1 0;
fifodata[`DROPPED] <= #1 0;
- fifodata[`UNDERRUN] <= #1 (check_next == 1) ? underrun[0] :
-
((check_next == 2) ? underrun[1] : 0);
- fifodata[`OVERRUN] <= #1 (check_next == 1) ? overrun[0] :
-
((check_next == 2) ? overrun[1] : 0);
+ fifodata[`UNDERRUN] <= #1 (check_next == 0) ? 1'b0 :
underrun[true_channel];
+ fifodata[`OVERRUN] <= #1 (check_next == 0) ? 1'b0 :
overrun[true_channel];
state <= #1 `TIMESTAMP;
end
@@ -119,6 +120,7 @@
begin
WR <= #1 0;
state <= #1 `IDLE;
+ chan_rdreq <= #1 0;
end
else if (read_length == payload_len - 4)
chan_rdreq <= #1 0;
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2007-09-07 17:47:53 UTC (rev 6352)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2007-09-07 19:58:21 UTC (rev 6353)
@@ -1,177 +1,179 @@
-//`include "../../firmware/include/fpga_regs_common.v"
-//`include "../../firmware/include/fpga_regs_standard.v"
-module rx_buffer_inband
- ( input usbclk,
- input bus_reset,
- input reset, // DSP side reset (used here), do not reset registers
- input reset_regs, //Only reset registers
- output [15:0] usbdata,
- input RD,
- output wire have_pkt_rdy,
- output reg rx_overrun,
- input wire [3:0] channels,
- input wire [15:0] ch_0,
- input wire [15:0] ch_1,
- input wire [15:0] ch_2,
- input wire [15:0] ch_3,
- input wire [15:0] ch_4,
- input wire [15:0] ch_5,
- input wire [15:0] ch_6,
- input wire [15:0] ch_7,
- input rxclk,
- input rxstrobe,
- input clear_status,
- input [6:0] serial_addr,
- input [31:0] serial_data,
- input serial_strobe,
- output wire [15:0] debugbus,
-
- //Connection with tx_inband
- input rx_WR,
- input [15:0] rx_databus,
- input rx_WR_done,
- output reg rx_WR_enabled,
- //signal strength
- input wire [31:0] rssi_0, input wire [31:0] rssi_1,
- input wire [31:0] rssi_2, input wire [31:0] rssi_3,
- input wire [1:0] tx_overrun, input wire [1:0] tx_underrun
- );
-
- parameter NUM_CHAN = 1;
- genvar i ;
-
- // FX2 Bug Fix
- reg [8:0] read_count;
- always @(negedge usbclk)
- if(bus_reset)
- read_count <= #1 9'd0;
- else if(RD & ~read_count[8])
- read_count <= #1 read_count + 9'd1;
- else
- read_count <= #1 RD ? read_count : 9'b0;
-
- // Time counter
- reg [31:0] adctime;
- always @(posedge rxclk)
- if (reset)
- adctime <= 0;
- else if (rxstrobe)
- adctime <= adctime + 1;
-
- // USB side fifo
- wire [11:0] rdusedw;
- wire [11:0] wrusedw;
- wire [15:0] fifodata;
- wire WR;
- wire have_space;
-
- fifo_4kx16_dc rx_usb_fifo (
- .aclr ( reset ),
- .data ( fifodata ),
- .rdclk ( ~usbclk ),
- .rdreq ( RD & ~read_count[8] ),
- .wrclk ( rxclk ),
- .wrreq ( WR ),
- .q ( usbdata ),
- .rdempty ( ),
- .rdusedw ( rdusedw ),
- .wrfull ( ),
- .wrusedw ( wrusedw ) );
-
- assign have_pkt_rdy = (rdusedw >= 12'd256);
- assign have_space = (wrusedw < 12'd760);
-
- // Rx side fifos
- wire chan_rdreq;
- wire [15:0] chan_fifodata;
- wire [9:0] chan_usedw;
- wire [NUM_CHAN:0] chan_empty;
- wire [3:0] rd_select;
- wire [NUM_CHAN:0] rx_full;
-
- packet_builder #(NUM_CHAN) rx_pkt_builer (
- .rxclk ( rxclk ),
- .reset ( reset ),
- .adctime ( adctime ),
- .channels ( 4'd1 ),
- .chan_rdreq ( chan_rdreq ),
- .chan_fifodata ( chan_fifodata ),
- .chan_empty ( chan_empty ),
- .rd_select ( rd_select ),
- .chan_usedw ( chan_usedw ),
- .WR ( WR ),
- .fifodata ( fifodata ),
- .have_space ( have_space ),
- .rssi_0(rssi_0), .rssi_1(rssi_1),
- .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug),
- .overrun(tx_overrun), .underrun(tx_underrun));
-
- // Detect overrun
- always @(posedge rxclk)
- if(reset)
- rx_overrun <= 1'b0;
- else if(rx_full[0])
- rx_overrun <= 1'b1;
- else if(clear_status)
- rx_overrun <= 1'b0;
-
- reg [6:0] test;
- always @(posedge rxclk)
- if (reset)
- test <= 0;
- else
- test <= test + 7'd1;
-
- // TODO write this genericly
- wire [15:0]ch[NUM_CHAN:0];
- assign ch[0] = ch_0;
-
- wire cmd_empty;
- always @(posedge rxclk)
- if(reset)
- rx_WR_enabled <= 1;
- else if(cmd_empty)
- rx_WR_enabled <= 1;
- else if(rx_WR_done)
- rx_WR_enabled <= 0;
-
- wire [15:0] dataout [0:NUM_CHAN];
- wire [9:0] usedw [0:NUM_CHAN];
-
- generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
- begin : generate_channel_fifos
- wire rdreq;
-
- assign rdreq = (rd_select == i) & chan_rdreq;
- assign chan_empty[i] = usedw[i] < 10'd126;
-
- fifo_2kx16 rx_chan_fifo (
- .aclr ( reset ),
- .clock ( rxclk ),
- .data ( ch[i] ),
- .rdreq ( rdreq ),
- .wrreq ( ~rx_full[i] & rxstrobe),
- .empty ( ),
- .full ( rx_full[i] ),
- .q ( dataout[i]),
- .usedw ( usedw[i] )
- );
- end
- endgenerate
- wire [7:0] debug;
- fifo_2kx16 rx_cmd_fifo (
- .aclr ( reset ),
- .clock ( rxclk ),
- .data ( rx_databus ),
- .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ),
- .wrreq ( rx_WR & rx_WR_enabled),
- .empty ( cmd_empty),
- .full ( rx_full[NUM_CHAN] ),
- .q ( dataout[NUM_CHAN]),
- .usedw ( usedw[NUM_CHAN] )
- );
- assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
- assign chan_fifodata = dataout[rd_select];
- assign chan_usedw = usedw[rd_select];
- assign debugbus = {wrusedw, have_space, RD, read_count[8], rxclk};
-endmodule
+//`include "../../firmware/include/fpga_regs_common.v"
+//`include "../../firmware/include/fpga_regs_standard.v"
+module rx_buffer_inband
+ ( input usbclk,
+ input bus_reset,
+ input reset, // DSP side reset (used here), do not reset registers
+ input reset_regs, //Only reset registers
+ output [15:0] usbdata,
+ input RD,
+ output wire have_pkt_rdy,
+ output reg rx_overrun,
+ input wire [3:0] channels,
+ input wire [15:0] ch_0,
+ input wire [15:0] ch_1,
+ input wire [15:0] ch_2,
+ input wire [15:0] ch_3,
+ input wire [15:0] ch_4,
+ input wire [15:0] ch_5,
+ input wire [15:0] ch_6,
+ input wire [15:0] ch_7,
+ input rxclk,
+ input rxstrobe,
+ input clear_status,
+ input [6:0] serial_addr,
+ input [31:0] serial_data,
+ input serial_strobe,
+ output wire [15:0] debugbus,
+
+ //Connection with tx_inband
+ input rx_WR,
+ input [15:0] rx_databus,
+ input rx_WR_done,
+ output reg rx_WR_enabled,
+ //signal strength
+ input wire [31:0] rssi_0, input wire [31:0] rssi_1,
+ input wire [31:0] rssi_2, input wire [31:0] rssi_3,
+ input wire [1:0] tx_overrun, input wire [1:0] tx_underrun
+ );
+
+ parameter NUM_CHAN = 1;
+ genvar i ;
+
+ // FX2 Bug Fix
+ reg [8:0] read_count;
+ always @(negedge usbclk)
+ if(bus_reset)
+ read_count <= #1 9'd0;
+ else if(RD & ~read_count[8])
+ read_count <= #1 read_count + 9'd1;
+ else
+ read_count <= #1 RD ? read_count : 9'b0;
+
+ // Time counter
+ reg [31:0] adctime;
+ always @(posedge rxclk)
+ if (reset)
+ adctime <= 0;
+ else if (rxstrobe)
+ adctime <= adctime + 1;
+
+ // USB side fifo
+ wire [11:0] rdusedw;
+ wire [11:0] wrusedw;
+ wire [15:0] fifodata;
+ wire WR;
+ wire have_space;
+
+ fifo_4k rx_usb_fifo (
+ .aclr ( reset ),
+ .data ( fifodata ),
+ .rdclk ( ~usbclk ),
+ .rdreq ( RD & ~read_count[8] ),
+ .wrclk ( rxclk ),
+ .wrreq ( WR ),
+ .q ( usbdata ),
+ .rdempty ( ),
+ .rdusedw ( rdusedw ),
+ .wrfull ( ),
+ .wrusedw ( wrusedw ) );
+
+ assign have_pkt_rdy = (rdusedw >= 12'd256);
+ assign have_space = (wrusedw < 12'd760);
+
+ // Rx side fifos
+ wire chan_rdreq;
+ wire [15:0] chan_fifodata;
+ wire [9:0] chan_usedw;
+ wire [NUM_CHAN:0] chan_empty;
+ wire [3:0] rd_select;
+ wire [NUM_CHAN:0] rx_full;
+
+ packet_builder #(NUM_CHAN) rx_pkt_builer (
+ .rxclk ( rxclk ),
+ .reset ( reset ),
+ .adctime ( adctime ),
+ .channels ( 4'd1 ),
+ .chan_rdreq ( chan_rdreq ),
+ .chan_fifodata ( chan_fifodata ),
+ .chan_empty ( chan_empty ),
+ .rd_select ( rd_select ),
+ .chan_usedw ( chan_usedw ),
+ .WR ( WR ),
+ .fifodata ( fifodata ),
+ .have_space ( have_space ),
+ .rssi_0(rssi_0), .rssi_1(rssi_1),
+ .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug),
+ .overrun(tx_overrun), .underrun(tx_underrun));
+
+ // Detect overrun
+ always @(posedge rxclk)
+ if(reset)
+ rx_overrun <= 1'b0;
+ else if(rx_full[0])
+ rx_overrun <= 1'b1;
+ else if(clear_status)
+ rx_overrun <= 1'b0;
+
+ reg [6:0] test;
+ always @(posedge rxclk)
+ if (reset)
+ test <= 0;
+ else
+ test <= test + 7'd1;
+
+ // TODO write this genericly
+ wire [15:0]ch[NUM_CHAN:0];
+ assign ch[0] = ch_0;
+
+ wire cmd_empty;
+ always @(posedge rxclk)
+ if(reset)
+ rx_WR_enabled <= 1;
+ else if(cmd_empty)
+ rx_WR_enabled <= 1;
+ else if(rx_WR_done)
+ rx_WR_enabled <= 0;
+
+ wire [15:0] dataout [0:NUM_CHAN];
+ wire [9:0] usedw [0:NUM_CHAN];
+ wire empty[0:NUM_CHAN];
+
+ generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
+ begin : generate_channel_fifos
+ wire rdreq;
+
+ assign rdreq = (rd_select == i) & chan_rdreq;
+ //assign chan_empty[i] = usedw[i] < 10'd126;
+ fifo_2k_1clk rx_chan_fifo (
+ .aclr ( reset ),
+ .clock ( rxclk ),
+ .data ( ch[i] ),
+ .rdreq ( rdreq ),
+ .wrreq ( ~rx_full[i] & rxstrobe),
+ .empty (empty[i]),
+ .full (rx_full[i]),
+ .q ( dataout[i]),
+ .usedw ( usedw[i]),
+ .almost_empty(chan_empty[i])
+ );
+ end
+ endgenerate
+ wire [7:0] debug;
+ fifo_2k_1clk rx_cmd_fifo (
+ .aclr ( reset ),
+ .clock ( rxclk ),
+ .data ( rx_databus ),
+ .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ),
+ .wrreq ( rx_WR & rx_WR_enabled),
+ .empty ( cmd_empty),
+ .full ( rx_full[NUM_CHAN] ),
+ .q ( dataout[NUM_CHAN]),
+ .usedw ( usedw[NUM_CHAN] )
+ );
+ assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
+ assign chan_fifodata = dataout[rd_select];
+ assign chan_usedw = usedw[rd_select];
+ assign debugbus = {rxstrobe, chan_rdreq, debug,
+ rx_full[0], chan_empty[0], empty[0],
have_space, RD, rxclk};
+endmodule
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/megacells/fifo_2k_1clk.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/megacells/fifo_2k_1clk.v
2007-09-07 17:47:53 UTC (rev 6352)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/megacells/fifo_2k_1clk.v
2007-09-07 19:58:21 UTC (rev 6353)
@@ -39,6 +39,7 @@
data,
rdreq,
wrreq,
+ almost_empty,
empty,
full,
q,
@@ -49,6 +50,7 @@
input [15:0] data;
input rdreq;
input wrreq;
+ output almost_empty;
output empty;
output full;
output [15:0] q;
@@ -56,12 +58,14 @@
wire [9:0] sub_wire0;
wire sub_wire1;
- wire [15:0] sub_wire2;
- wire sub_wire3;
+ wire sub_wire2;
+ wire [15:0] sub_wire3;
+ wire sub_wire4;
wire [9:0] usedw = sub_wire0[9:0];
wire empty = sub_wire1;
- wire [15:0] q = sub_wire2[15:0];
- wire full = sub_wire3;
+ wire almost_empty = sub_wire2;
+ wire [15:0] q = sub_wire3[15:0];
+ wire full = sub_wire4;
scfifo scfifo_component (
.rdreq (rdreq),
@@ -71,17 +75,18 @@
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
- .q (sub_wire2),
- .full (sub_wire3)
+ .almost_empty (sub_wire2),
+ .q (sub_wire3),
+ .full (sub_wire4)
// synopsys translate_off
,
- .almost_empty (),
.sclr (),
.almost_full ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
+ scfifo_component.almost_empty_value = 128,
scfifo_component.intended_device_family = "Cyclone",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
scfifo_component.lpm_numwords = 1024,
@@ -99,8 +104,8 @@
// ============================================================
// CNX file retrieval info
// ============================================================
-// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "128"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
@@ -128,6 +133,7 @@
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "128"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
@@ -139,6 +145,7 @@
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
+// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
@@ -155,12 +162,13 @@
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0
+// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk.cmp TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk_waveforms.html FALSE
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-09-07 17:47:53 UTC (rev 6352)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-09-07 19:58:21 UTC (rev 6353)
@@ -164,7 +164,7 @@
.reg_data_out(reg_data_out),
.reg_data_in(reg_data_in),
.reg_io_enable(reg_io_enable),
- .debugbus(tx_debugbus),
+ .debugbus(),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
.rssi_3(rssi_3), .threshhold(rssi_threshhold));
`else
@@ -281,7 +281,7 @@
.rx_databus(rx_databus),
.rx_WR_done(rx_WR_done),
.rx_WR_enabled(rx_WR_enabled),
- .debugbus(rx_debugbus),
+ .debugbus(tx_debugbus),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), .rssi_3(rssi_3),
.tx_overrun(tx_overrun), .tx_underrun(tx_underrun));
`else
@@ -296,8 +296,7 @@
.ch_6(ch6rx),.ch_7(ch7rx),
.rxclk(clk64),.rxstrobe(hb_strobe),
.clear_status(clear_status),
-
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)/*,
- .debugbus(rx_debugbus)*/);
+
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
`endif
`ifdef RX_EN_0
| [Prev in Thread] |
Current Thread |
[Next in Thread] |
- [Commit-gnuradio] r6353 - in gnuradio/branches/developers/zhuochen/inband/usrp/fpga: inband_lib megacells toplevel/usrp_inband_usb,
zhuochen <=