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[Commit-gnuradio] r6639 - in gnuradio/branches/features/inband-usb/usrp/
|
From: |
gnychis |
|
Subject: |
[Commit-gnuradio] r6639 - in gnuradio/branches/features/inband-usb/usrp/fpga: inband_lib rbf/rev2 rbf/rev4 sdr_lib toplevel/usrp_inband_usb |
|
Date: |
Tue, 16 Oct 2007 16:41:29 -0600 (MDT) |
Author: gnychis
Date: 2007-10-16 16:41:29 -0600 (Tue, 16 Oct 2007)
New Revision: 6639
Added:
gnuradio/branches/features/inband-usb/usrp/fpga/rbf/rev2/std_inband.rbf
gnuradio/branches/features/inband-usb/usrp/fpga/rbf/rev4/std_inband.rbf
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/cmd_reader.v
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/packet_builder.v
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/register_io.v
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/rx_buffer_inband.v
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/tx_buffer_inband.v
gnuradio/branches/features/inband-usb/usrp/fpga/sdr_lib/master_control.v
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
Log:
Merge of -r6443:6638 from branches/developers/zhuochen/inband to features
branch.
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/cmd_reader.v
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/cmd_reader.v
2007-10-16 22:36:47 UTC (rev 6638)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/cmd_reader.v
2007-10-16 22:41:29 UTC (rev 6639)
@@ -18,7 +18,9 @@
output reg [31:0] reg_data_in,
output reg [6:0] reg_addr,
output reg [1:0] reg_io_enable,
- output wire [14:0] debug
+ output wire [14:0] debug,
+ output reg stop,
+ output reg [15:0] stop_time
);
// States
@@ -74,6 +76,7 @@
reg_io_enable <= 0;
reg_data_in <= 0;
reg_addr <= 0;
+ stop <= 0;
end
else case (state)
IDLE : begin
@@ -119,6 +122,7 @@
reg_io_enable <= 0;
rx_WR <= 0;
rx_WR_done <= 1;
+ stop <= 0;
if (payload_read == payload)
begin
skip <= 1;
@@ -279,9 +283,9 @@
DELAY : begin
rdreq <= 0;
- value1 <= value1 + 32'd1;
- if (value0[15:0] == value1[15:0])
- state <= TEST;
+ stop <= 1;
+ stop_time <= value0[15:0];
+ state <= TEST;
end
default : begin
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/packet_builder.v
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/packet_builder.v
2007-10-16 22:36:47 UTC (rev 6638)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/packet_builder.v
2007-10-16 22:41:29 UTC (rev 6639)
@@ -16,7 +16,7 @@
input have_space,
input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire
[31:0]rssi_2,
input wire [31:0]rssi_3, output wire [7:0] debugbus,
- input [NUM_CHAN:0] overrun, input [NUM_CHAN:0] underrun);
+ input [NUM_CHAN:0] underrun);
// States
@@ -39,6 +39,7 @@
`define UNDERRUN 14
`define OVERRUN 15
+ reg [NUM_CHAN:0] overrun;
reg [2:0] state;
reg [8:0] read_length;
reg [8:0] payload_len;
@@ -58,6 +59,7 @@
begin
if (reset)
begin
+ overrun <= 0;
WR <= 0;
rd_select <= 0;
chan_rdreq <= 0;
@@ -68,15 +70,24 @@
else case (state)
`IDLE: begin
chan_rdreq <= #1 0;
- if (have_space)
+ //check if the channel is full
+ if(~chan_empty[check_next])
begin
- if(~chan_empty[check_next])
- begin
+ if (have_space)
+ begin
+ //transmit if the usb buffer
have space
state <= #1 `HEADER1;
- rd_select <= #1 check_next;
- end
- check_next <= #1 (check_next ==
channels ? 4'd0 : check_next + 4'd1);
- end
+ overrun[check_next] <= 0;
+ end
+ else
+ begin
+ //wait if the usb buffer is
full and set overrun
+ state <= #1 `IDLE;
+ overrun[check_next] <= 1;
+ end
+ rd_select <= #1 check_next;
+ end
+ check_next <= #1 (check_next == channels ? 4'd0
: check_next + 4'd1);
end
`HEADER1: begin
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/register_io.v
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/register_io.v
2007-10-16 22:36:47 UTC (rev 6638)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/register_io.v
2007-10-16 22:41:29 UTC (rev 6639)
@@ -1,15 +1,108 @@
module register_io
- (input clk, input reset, input wire [1:0] enable, input wire [6:0]
addr,
- input wire [31:0] datain, output reg [31:0] dataout, output wire
[15:0] debugbus,
- input wire [31:0] rssi_0, input wire [31:0] rssi_1,
- input wire [31:0] rssi_2, input wire [31:0] rssi_3,
- output wire [31:0] threshhold, output wire [31:0] rssi_wait);
-
+ (clk, reset, enable, addr, datain, dataout, debugbus, addr_wr, data_wr,
strobe_wr,
+ rssi_0, rssi_1, rssi_2, rssi_3, threshhold, rssi_wait, reg_0, reg_1,
reg_2, reg_3,
+ atr_tx_delay, atr_rx_delay, master_controls, debug_en, interp_rate,
decim_rate,
+ atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1,
atr_rxval_1,
+ atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3,
atr_rxval_3,
+ txa_refclk, txb_refclk, rxa_refclk, rxb_refclk, misc, txmux);
+
+ input clk;
+ input reset;
+ input wire [1:0] enable;
+ input wire [6:0] addr;
+ input wire [31:0] datain;
+ output reg [31:0] dataout;
+ output wire [15:0] debugbus;
+ output reg [6:0] addr_wr;
+ output reg [31:0] data_wr;
+ output wire strobe_wr;
+ input wire [31:0] rssi_0;
+ input wire [31:0] rssi_1;
+ input wire [31:0] rssi_2;
+ input wire [31:0] rssi_3;
+ output wire [31:0] threshhold;
+ output wire [31:0] rssi_wait;
+ input wire [15:0] reg_0;
+ input wire [15:0] reg_1;
+ input wire [15:0] reg_2;
+ input wire [15:0] reg_3;
+ input wire [11:0] atr_tx_delay;
+ input wire [11:0] atr_rx_delay;
+ input wire [7:0] master_controls;
+ input wire [3:0] debug_en;
+ input wire [15:0] atr_mask_0;
+ input wire [15:0] atr_txval_0;
+ input wire [15:0] atr_rxval_0;
+ input wire [15:0] atr_mask_1;
+ input wire [15:0] atr_txval_1;
+ input wire [15:0] atr_rxval_1;
+ input wire [15:0] atr_mask_2;
+ input wire [15:0] atr_txval_2;
+ input wire [15:0] atr_rxval_2;
+ input wire [15:0] atr_mask_3;
+ input wire [15:0] atr_txval_3;
+ input wire [15:0] atr_rxval_3;
+ input wire [7:0] txa_refclk;
+ input wire [7:0] txb_refclk;
+ input wire [7:0] rxa_refclk;
+ input wire [7:0] rxb_refclk;
+ input wire [7:0] interp_rate;
+ input wire [7:0] decim_rate;
+ input wire [7:0] misc;
+ input wire [31:0] txmux;
+
+ wire [31:0] bundle[43:0];
+ assign bundle[0] = 32'hFFFFFFFF;
+ assign bundle[1] = 32'hFFFFFFFF;
+ assign bundle[2] = {20'd0, atr_tx_delay};
+ assign bundle[3] = {20'd0, atr_rx_delay};
+ assign bundle[4] = {24'sd0, master_controls};
+ assign bundle[5] = 32'hFFFFFFFF;
+ assign bundle[6] = 32'hFFFFFFFF;
+ assign bundle[7] = 32'hFFFFFFFF;
+ assign bundle[8] = 32'hFFFFFFFF;
+ assign bundle[9] = {15'd0, reg_0};
+ assign bundle[10] = {15'd0, reg_1};
+ assign bundle[11] = {15'd0, reg_2};
+ assign bundle[12] = {15'd0, reg_3};
+ assign bundle[13] = {15'd0, misc};
+ assign bundle[14] = {28'd0, debug_en};
+ assign bundle[15] = 32'hFFFFFFFF;
+ assign bundle[16] = 32'hFFFFFFFF;
+ assign bundle[17] = 32'hFFFFFFFF;
+ assign bundle[18] = 32'hFFFFFFFF;
+ assign bundle[19] = 32'hFFFFFFFF;
+ assign bundle[20] = {16'd0, atr_mask_0};
+ assign bundle[21] = {16'd0, atr_txval_0};
+ assign bundle[22] = {16'd0, atr_rxval_0};
+ assign bundle[23] = {16'd0, atr_mask_1};
+ assign bundle[24] = {16'd0, atr_txval_1};
+ assign bundle[25] = {16'd0, atr_rxval_1};
+ assign bundle[26] = {16'd0, atr_mask_2};
+ assign bundle[27] = {16'd0, atr_txval_2};
+ assign bundle[28] = {16'd0, atr_rxval_2};
+ assign bundle[29] = {16'd0, atr_mask_3};
+ assign bundle[30] = {16'd0, atr_txval_3};
+ assign bundle[31] = {16'd0, atr_rxval_3};
+ assign bundle[32] = {24'd0, interp_rate};
+ assign bundle[33] = {24'd0, decim_rate};
+ assign bundle[34] = 32'hFFFFFFFF;
+ assign bundle[35] = 32'hFFFFFFFF;
+ assign bundle[36] = 32'hFFFFFFFF;
+ assign bundle[37] = 32'hFFFFFFFF;
+ assign bundle[38] = 32'hFFFFFFFF;
+ assign bundle[39] = txmux;
+ assign bundle[40] = {24'd0, txa_refclk};
+ assign bundle[41] = {24'd0, rxa_refclk};
+ assign bundle[42] = {24'd0, txb_refclk};
+ assign bundle[43] = {24'd0, rxb_refclk};
+
reg strobe;
wire [31:0] out[7:0];
assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]};
assign threshhold = out[1];
assign rssi_wait = out[2];
+ assign strobe_wr = strobe;
always @(*)
if (reset | ~enable[1])
@@ -22,41 +115,39 @@
if (enable[0])
begin
//read
- if (addr == 7'd9)
- dataout <= rssi_0;
- else if (addr == 7'd10)
- dataout <= rssi_1;
- else if (addr == 7'd11)
- dataout <= rssi_2;
- else if (addr == 7'd12)
- dataout <= rssi_3;
- else
- dataout <= out[addr[2:0]];
- strobe <= 0;
- end
+ if (addr <= 7'd43)
+ dataout <= bundle[addr];
+ else if (addr <= 7'd57 && addr >= 7'd50)
+ dataout <= out[addr-7'd50];
+ else
+ dataout <= 32'hFFFFFFFF;
+ strobe <= 0;
+ end
else
begin
//write
dataout <= dataout;
strobe <= 1;
+ data_wr <= datain;
+ addr_wr <= addr;
end
end
//register declarations
- setting_reg #(0) setting_reg0(.clock(clk),.reset(reset),
+ setting_reg #(50) setting_reg0(.clock(clk),.reset(reset),
.strobe(strobe),.addr(addr),.in(datain),.out(out[0]));
- setting_reg #(1) setting_reg1(.clock(clk),.reset(reset),
+ setting_reg #(51) setting_reg1(.clock(clk),.reset(reset),
.strobe(strobe),.addr(addr),.in(datain),.out(out[1]));
- setting_reg #(2) setting_reg2(.clock(clk),.reset(reset),
+ setting_reg #(52) setting_reg2(.clock(clk),.reset(reset),
.strobe(strobe),.addr(addr),.in(datain),.out(out[2]));
- setting_reg #(3) setting_reg3(.clock(clk),.reset(reset),
+ setting_reg #(53) setting_reg3(.clock(clk),.reset(reset),
.strobe(strobe),.addr(addr),.in(datain),.out(out[3]));
- setting_reg #(4) setting_reg4(.clock(clk),.reset(reset),
+ setting_reg #(54) setting_reg4(.clock(clk),.reset(reset),
.strobe(strobe),.addr(addr),.in(datain),.out(out[4]));
- setting_reg #(5) setting_reg5(.clock(clk),.reset(reset),
+ setting_reg #(55) setting_reg5(.clock(clk),.reset(reset),
.strobe(strobe),.addr(addr),.in(datain),.out(out[5]));
- setting_reg #(6) setting_reg6(.clock(clk),.reset(reset),
+ setting_reg #(56) setting_reg6(.clock(clk),.reset(reset),
.strobe(strobe),.addr(addr),.in(datain),.out(out[6]));
- setting_reg #(7) setting_reg7(.clock(clk),.reset(reset),
+ setting_reg #(57) setting_reg7(.clock(clk),.reset(reset),
.strobe(strobe),.addr(addr),.in(datain),.out(out[7]));
endmodule
\ No newline at end of file
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/rx_buffer_inband.v
===================================================================
---
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/rx_buffer_inband.v
2007-10-16 22:36:47 UTC (rev 6638)
+++
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/rx_buffer_inband.v
2007-10-16 22:41:29 UTC (rev 6639)
@@ -34,7 +34,7 @@
//signal strength
input wire [31:0] rssi_0, input wire [31:0] rssi_1,
input wire [31:0] rssi_2, input wire [31:0] rssi_3,
- input wire [1:0] tx_overrun, input wire [1:0] tx_underrun
+ input wire [1:0] tx_underrun
);
parameter NUM_CHAN = 1;
@@ -104,7 +104,7 @@
.have_space ( have_space ),
.rssi_0(rssi_0), .rssi_1(rssi_1),
.rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug),
- .overrun(tx_overrun), .underrun(tx_underrun));
+ .underrun(tx_underrun));
// Detect overrun
always @(posedge rxclk)
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/tx_buffer_inband.v
===================================================================
---
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-10-16 22:36:47 UTC (rev 6638)
+++
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-10-16 22:41:29 UTC (rev 6639)
@@ -5,7 +5,7 @@
clear_status, tx_empty, debugbus,
rx_databus, rx_WR, rx_WR_done, rx_WR_enabled, reg_io_enable,
reg_data_in, reg_data_out, reg_addr, rssi_0, rssi_1, rssi_2,
- rssi_3, rssi_wait, threshhold, tx_underrun
+ rssi_3, rssi_wait, threshhold, tx_underrun, stop, stop_time
);
parameter NUM_CHAN = 2 ;
@@ -55,7 +55,10 @@
output wire [6:0] reg_addr;
output wire [1:0] reg_io_enable;
output wire [NUM_CHAN-1:0] tx_underrun;
-
+ /*stoppage*/
+ output wire stop;
+ output wire [15:0] stop_time;
+
/* To generate channel readers */
genvar i ;
@@ -215,7 +218,9 @@
.reg_data_out (reg_data_out),
.reg_addr
(reg_addr),
.reg_io_enable (reg_io_enable),
- .debug (debug)
+ .debug (debug),
+ .stop (stop),
+ .stop_time
(stop_time)
);
Copied: gnuradio/branches/features/inband-usb/usrp/fpga/rbf/rev2/std_inband.rbf
(from rev 6638,
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/rbf/rev2/std_inband.rbf)
===================================================================
(Binary files differ)
Copied: gnuradio/branches/features/inband-usb/usrp/fpga/rbf/rev4/std_inband.rbf
(from rev 6638,
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/rbf/rev4/std_inband.rbf)
===================================================================
(Binary files differ)
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/sdr_lib/master_control.v
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/sdr_lib/master_control.v
2007-10-16 22:36:47 UTC (rev 6638)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/sdr_lib/master_control.v
2007-10-16 22:41:29 UTC (rev 6639)
@@ -23,22 +23,64 @@
// Clock, enable, and reset controls for whole system
module master_control
- ( input master_clk, input usbclk,
- input wire [6:0] serial_addr, input wire [31:0] serial_data, input wire
serial_strobe,
- output tx_bus_reset, output rx_bus_reset,
- output wire tx_dsp_reset, output wire rx_dsp_reset,
- output wire enable_tx, output wire enable_rx,
- output wire [7:0] interp_rate, output wire [7:0] decim_rate,
- output tx_sample_strobe, output strobe_interp,
- output rx_sample_strobe, output strobe_decim,
- input tx_empty,
- input wire [15:0] debug_0,input wire [15:0] debug_1,input wire [15:0]
debug_2,input wire [15:0] debug_3,
- output wire [15:0] reg_0, output wire [15:0] reg_1, output wire [15:0]
reg_2, output wire [15:0] reg_3
- );
-
+ (master_clk, usbclk, serial_addr, serial_data, serial_strobe, tx_bus_reset,
rx_bus_reset,
+ tx_dsp_reset, rx_dsp_reset, enable_tx, enable_rx, interp_rate, decim_rate,
+ tx_sample_strobe, strobe_interp, rx_sample_strobe, strobe_decim,
+ tx_empty, debug_0, debug_1, debug_2, debug_3, reg_0, reg_1, reg_2, reg_3,
+ atr_tx_delay, atr_rx_delay, master_controls, debug_en,
+ atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1, atr_rxval_1,
+ atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3, atr_rxval_3,
+ txa_refclk, txb_refclk, rxa_refclk, rxb_refclk);
+
+ input master_clk;
+ input usbclk;
+ input wire [6:0] serial_addr;
+ input wire [31:0] serial_data;
+ input wire serial_strobe;
+ output tx_bus_reset;
+ output rx_bus_reset;
+ output wire tx_dsp_reset;
+ output wire rx_dsp_reset;
+ output wire enable_tx;
+ output wire enable_rx;
+ output wire [7:0] interp_rate;
+ output wire [7:0] decim_rate;
+ output tx_sample_strobe;
+ output strobe_interp;
+ output rx_sample_strobe;
+ output strobe_decim;
+ input tx_empty;
+ input wire [15:0] debug_0;
+ input wire [15:0] debug_1;
+ input wire [15:0] debug_2;
+ input wire [15:0] debug_3;
+ output wire [15:0] reg_0;
+ output wire [15:0] reg_1;
+ output wire [15:0] reg_2;
+ output wire [15:0] reg_3;
+ output wire [11:0] atr_tx_delay;
+ output wire [11:0] atr_rx_delay;
+ output wire [7:0] master_controls;
+ output wire [3:0] debug_en;
+ output wire [15:0] atr_mask_0;
+ output wire [15:0] atr_txval_0;
+ output wire [15:0] atr_rxval_0;
+ output wire [15:0] atr_mask_1;
+ output wire [15:0] atr_txval_1;
+ output wire [15:0] atr_rxval_1;
+ output wire [15:0] atr_mask_2;
+ output wire [15:0] atr_txval_2;
+ output wire [15:0] atr_rxval_2;
+ output wire [15:0] atr_mask_3;
+ output wire [15:0] atr_txval_3;
+ output wire [15:0] atr_rxval_3;
+ output wire [7:0] txa_refclk;
+ output wire [7:0] txb_refclk;
+ output wire [7:0] rxa_refclk;
+ output wire [7:0] rxb_refclk;
+
// FIXME need a separate reset for all control settings
// Master Controls assignments
- wire [7:0] master_controls;
setting_reg #(`FR_MASTER_CTRL)
sr_mstr_ctrl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(master_controls));
assign enable_tx = master_controls[0];
assign enable_rx = master_controls[1];
@@ -79,9 +121,8 @@
assign tx_bus_reset = tx_reset_bus_sync2;
assign rx_bus_reset = rx_reset_bus_sync2;
- wire [7:0] txa_refclk, rxa_refclk, txb_refclk, rxb_refclk;
wire txaclk,txbclk,rxaclk,rxbclk;
- wire [3:0] debug_en, txcvr_ctrl;
+ wire [3:0] txcvr_ctrl;
wire [31:0] txcvr_rxlines, txcvr_txlines;
@@ -114,8 +155,6 @@
wire transmit_now;
wire atr_ctl;
- wire [11:0] atr_tx_delay, atr_rx_delay;
- wire [15:0] atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1,
atr_rxval_1, atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3,
atr_rxval_3;
setting_reg #(`FR_ATR_MASK_0)
sr_atr_mask_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_0));
setting_reg #(`FR_ATR_TXVAL_0)
sr_atr_txval_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_0));
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
===================================================================
---
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-10-16 22:36:47 UTC (rev 6638)
+++
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-10-16 22:41:29 UTC (rev 6639)
@@ -97,8 +97,6 @@
// Tri-state bus macro
bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) );
- assign clk64 = master_clk;
-
wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx;
wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx;
@@ -129,19 +127,7 @@
assign bb_tx_q0 = ch1tx;
assign bb_tx_i1 = ch2tx;
assign bb_tx_q1 = ch3tx;
-
-wire [6:0] reg_addr;
-wire [31:0] reg_data_out;
-wire [31:0] reg_data_in;
-wire [1:0] reg_io_enable;
-wire [31:0] rssi_threshhold;
-wire [31:0] rssi_wait;
-register_io register_control
-(.clk(clk64),.reset(1'b0),.enable(reg_io_enable),.addr(reg_addr),.datain(reg_data_in),
- .dataout(reg_data_out),.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
- .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait));
-wire [1:0] tx_overrun;
wire [1:0] tx_underrun;
`ifdef TX_IN_BAND
@@ -166,7 +152,8 @@
.reg_io_enable(reg_io_enable),
.debugbus(),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
- .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait));
+ .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
+ .stop(stop), .stop_time(stop_time));
`else
tx_buffer tx_buffer
( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
@@ -283,7 +270,7 @@
.rx_WR_enabled(rx_WR_enabled),
.debugbus(tx_debugbus),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), .rssi_3(rssi_3),
- .tx_overrun(tx_overrun), .tx_underrun(tx_underrun));
+ .tx_underrun(tx_underrun));
`else
rx_buffer rx_buffer
( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
@@ -357,11 +344,74 @@
serial_io serial_io
( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
.enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
-
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .serial_addr(addr_db),.serial_data(data_db),.serial_strobe(strobe_db),
.readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a),
.readback_4(rssi_0),.readback_5(rssi_1),.readback_6(rssi_2),.readback_7(rssi_3)
);
+ wire [6:0] reg_addr;
+ wire [31:0] reg_data_out;
+ wire [31:0] reg_data_in;
+ wire [1:0] reg_io_enable;
+ wire [31:0] rssi_threshhold;
+ wire [31:0] rssi_wait;
+ wire [6:0] addr_wr;
+ wire [31:0] data_wr;
+ wire strobe_wr;
+ wire [6:0] addr_db;
+ wire [31:0] data_db;
+ wire strobe_db;
+ assign serial_strobe = strobe_db | strobe_wr;
+ assign serial_addr = (strobe_db)? (addr_db) : (addr_wr);
+ assign serial_data = (strobe_db)? (data_db) : (addr_db);
+
+ //wires for register connection
+ wire [11:0] atr_tx_delay;
+ wire [11:0] atr_rx_delay;
+ wire [7:0] master_controls;
+ wire [3:0] debug_en;
+ wire [15:0] atr_mask_0;
+ wire [15:0] atr_txval_0;
+ wire [15:0] atr_rxval_0;
+ wire [15:0] atr_mask_1;
+ wire [15:0] atr_txval_1;
+ wire [15:0] atr_rxval_1;
+ wire [15:0] atr_mask_2;
+ wire [15:0] atr_txval_2;
+ wire [15:0] atr_rxval_2;
+ wire [15:0] atr_mask_3;
+ wire [15:0] atr_txval_3;
+ wire [15:0] atr_rxval_3;
+ wire [7:0] txa_refclk;
+ wire [7:0] txb_refclk;
+ wire [7:0] rxa_refclk;
+ wire [7:0] rxb_refclk;
+ register_io register_control
+
(.clk(clk64),.reset(1'b0),.enable(reg_io_enable),.addr(reg_addr),.datain(reg_data_in),
+ .dataout(reg_data_out), .data_wr(data_wr), .addr_wr(addr_wr),
.strobe_wr(strobe_wr),
+ .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
+ .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
+ .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
+ .interp_rate(interp_rate), .decim_rate(decim_rate), .misc(settings),
+ .txmux({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}),
+ .atr_tx_delay(atr_tx_delay), .atr_rx_delay(atr_rx_delay),
.master_controls(master_controls),
+ .debug_en(debug_en), .atr_mask_0(atr_mask_0),
.atr_txval_0(atr_txval_0), .atr_rxval_0(atr_rxval_0),
+ .atr_mask_1(atr_mask_1), .atr_txval_1(atr_txval_1),
.atr_rxval_1(atr_rxval_1),
+ .atr_mask_2(atr_mask_2), .atr_txval_2(atr_txval_2),
.atr_rxval_2(atr_rxval_2),
+ .atr_mask_3(atr_mask_3), .atr_txval_3(atr_txval_3),
.atr_rxval_3(atr_rxval_3),
+ .txa_refclk(txa_refclk), .txb_refclk(txb_refclk),
.rxa_refclk(rxa_refclk), .rxb_refclk(rxb_refclk));
+
+ reg [15:0] timestop;
+ wire stop;
+ wire [15:0] stop_time;
+ assign clk64 = (timestop == 0) ? master_clk : 0;
+ always @(posedge master_clk)
+ if (timestop[15:0] != 0)
+ timestop <= timestop - 16'd1;
+ else if (stop)
+ timestop <= stop_time;
+
+
wire [15:0] reg_0,reg_1,reg_2,reg_3;
master_control master_control
( .master_clk(clk64),.usbclk(usbclk),
@@ -372,11 +422,14 @@
.interp_rate(interp_rate),.decim_rate(decim_rate),
.tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
.rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
- .tx_empty(tx_empty),
- //.debug_0(rx_a_a),.debug_1(ddc0_in_i),
- .debug_0(tx_debugbus),.debug_1(tx_debugbus),
-
.debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,(tx_underrun
== 0),rx_overrun,decim_rate}),
- .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
+ .tx_empty(tx_empty),
.reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
+ .atr_tx_delay(atr_tx_delay), .atr_rx_delay(atr_rx_delay),
+ .master_controls(master_controls), .debug_en(debug_en),
+ .atr_mask_0(atr_mask_0), .atr_txval_0(atr_txval_0),
.atr_rxval_0(atr_rxval_0),
+ .atr_mask_1(atr_mask_1), .atr_txval_1(atr_txval_1),
.atr_rxval_1(atr_rxval_1),
+ .atr_mask_2(atr_mask_2), .atr_txval_2(atr_txval_2),
.atr_rxval_2(atr_rxval_2),
+ .atr_mask_3(atr_mask_3), .atr_txval_3(atr_txval_3),
.atr_rxval_3(atr_rxval_3),
+ .txa_refclk(txa_refclk), .txb_refclk(txb_refclk),
.rxa_refclk(rxa_refclk), .rxb_refclk(rxb_refclk));
io_pins io_pins
(.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b),
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- [Commit-gnuradio] r6639 - in gnuradio/branches/features/inband-usb/usrp/fpga: inband_lib rbf/rev2 rbf/rev4 sdr_lib toplevel/usrp_inband_usb,
gnychis <=