[Commit-gnuradio] r7330 - gnuradio/branches/developers/jcorgan/xcvr2450/gr-usrp/src

[jcorgan]

Author: jcorgan
Date: 2008-01-03 00:48:02 -0700 (Thu, 03 Jan 2008)
New Revision: 7330

Modified:
   gnuradio/branches/developers/jcorgan/xcvr2450/gr-usrp/src/db_xcvr2450.py
Log:
Prettify multi-line statements

Modified: 
gnuradio/branches/developers/jcorgan/xcvr2450/gr-usrp/src/db_xcvr2450.py
===================================================================
--- gnuradio/branches/developers/jcorgan/xcvr2450/gr-usrp/src/db_xcvr2450.py    
2008-01-03 04:25:40 UTC (rev 7329)
+++ gnuradio/branches/developers/jcorgan/xcvr2450/gr-usrp/src/db_xcvr2450.py    
2008-01-03 07:48:02 UTC (rev 7330)
@@ -130,19 +130,19 @@
         
     # Standby (2)
     def set_reg_standby(self):
-        self.reg_standby = \
-            (self.mimo<<17) | \
-            (1<<16)         | \
-            (1<<6)          | \
-            (1<<5)          | \
-            (1<<4)          | 2
+        self.reg_standby = (
+            (self.mimo<<17) | 
+            (1<<16)         | 
+            (1<<6)          | 
+            (1<<5)          | 
+            (1<<4)          | 2)
         self._send_reg(self.reg_standby)
 
     # Integer-Divider Ratio (3)
     def set_reg_int_divider(self):
-        self.reg_int_divider = \
-            ((self.frac_div & 0x03)<<16) | \
-            (self.int_div<<4)            | 3
+        self.reg_int_divider = (
+            ((self.frac_div & 0x03)<<16) | 
+            (self.int_div<<4)            | 3)
         self._send_reg(self.reg_int_divider)
 
     # Fractional-Divider Ratio (4)
@@ -163,15 +163,15 @@
                self.highband = 0
                self.five_gig = 0
 
-        self.reg_bandselpll = \
-            (self.mimo<<17)      | \
-            (1<<16)              | \
-            (1<<15)              | \
-            (self.auto_bsw<<11)  | \
-            (self.highband<<10)  | \
-            (self.cp_current<<9) | \
-            (self.ref_div<<5)    | \
-            (self.five_gig<<4)   | 5
+        self.reg_bandselpll = (
+            (self.mimo<<17)      |
+            (1<<16)              |
+            (1<<15)              |
+            (self.auto_bsw<<11)  |
+            (self.highband<<10)  |
+            (self.cp_current<<9) |
+            (self.ref_div<<5)    |
+            (self.five_gig<<4)   | 5)
         self._send_reg(self.reg_bandselpll)
      
 
@@ -184,43 +184,43 @@
 
     # Lowpass Filter (7)
     def set_reg_lpf(self):
-        self.reg_lpf = \
-            (self.rssi_hbw<<15)  | \
-            (self.txlpf_bw<<10)  | \
-            (self.rxlpf_bw<<9)   | \
-            (self.rxlpf_fine<<4) | 7
+        self.reg_lpf = (
+            (self.rssi_hbw<<15)  |
+            (self.txlpf_bw<<10)  |
+            (self.rxlpf_bw<<9)   |
+            (self.rxlpf_fine<<4) | 7)
         self._send_reg(self.reg_lpf)
 
 
     # Rx Control/RSSI (8)
     def set_reg_rxrssi_ctrl(self):
-        self.reg_rxrssi_ctrl = \
-            (self.rxvga_ser<<16)  | \
-            (self.rssi_range<<15) | \
-            (self.rssi_mode<<14)  | \
-            (self.rssi_mux<<12)   | \
-            (1<<9)                | \
-            (self.rx_hpf<<6)      | \
-            (1<<4) | 8
+        self.reg_rxrssi_ctrl = (
+            (self.rxvga_ser<<16)  |
+            (self.rssi_range<<15) |
+            (self.rssi_mode<<14)  |
+            (self.rssi_mux<<12)   |
+            (1<<9)                |
+            (self.rx_hpf<<6)      |
+            (1<<4)               | 8)
         self._send_reg(self.reg_rxrssi_ctrl)
 
 
     # Tx Linearity/Baseband Gain (9)
     def set_reg_txlin_gain(self):
-        self.reg_txlin_gain = \
-            (self.txvga_ser<<14)     | \
-            (self.tx_driver_lin<<12) | \
-            (self.tx_vga_lin<<10)    | \
-            (self.tx_upconv_lin<<6)  | \
-            (self.tx_bb_gain<<4)     | 9
+        self.reg_txlin_gain = (
+            (self.txvga_ser<<14)     |
+            (self.tx_driver_lin<<12) |
+            (self.tx_vga_lin<<10)    |
+            (self.tx_upconv_lin<<6)  |
+            (self.tx_bb_gain<<4)     | 9)
         self._send_reg(self.reg_txlin_gain)
 
 
     # PA Bias DAC (10)
     def set_reg_pabias(self):
-        self.reg_pabias = \
-            (self.pabias_delay<<10) | \
-            (self.pabias<<4)        | 10
+        self.reg_pabias = (
+            (self.pabias_delay<<10) |
+            (self.pabias<<4)        | 10)
         self._send_reg(self.reg_pabias)