[Commit-gnuradio] r7341 - in usrp2/trunk/fpga/top: u2_basic u2_fpga

[matt]

Author: matt
Date: 2008-01-04 13:31:06 -0700 (Fri, 04 Jan 2008)
New Revision: 7341

Modified:
   usrp2/trunk/fpga/top/u2_basic/u2_basic.v
   usrp2/trunk/fpga/top/u2_fpga/u2_fpga.ise
Log:
moved debug buses around


Modified: usrp2/trunk/fpga/top/u2_basic/u2_basic.v
===================================================================
--- usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2008-01-04 17:59:47 UTC (rev 
7340)
+++ usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2008-01-04 20:31:06 UTC (rev 
7341)
@@ -144,11 +144,9 @@
    wire        bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, 
proc_int, overrun, underrun, uart_int;
 
    wire [31:0]         debug_gpio_0, debug_gpio_1;
-   wire [31:0]         debug_rx, debug_rx_1, debug_rx_2;
-   wire [31:0]         debug_wb, debug_txmacfifo_in, debug_txmacfifo_out, 
debug_bufpool, debug_bufpool2;
-   wire [15:0]         debug_gmii_1, debug_gmii_2;
    wire [31:0]         atr_lines;
-   
+
+   wire [31:0]         debug_rx;
    // 
///////////////////////////////////////////////////////////////////////////////////////////////
    // Wishbone Single Master INTERCON
    parameter   dw = 32;  // Data bus width
@@ -588,18 +586,24 @@
    // 
/////////////////////////////////////////////////////////////////////////////////////////
    // Debug Pins
 
-   assign      debug_rx_1 = 
{uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV,
+   // Assign various commonly used debug buses.  Try to always have uart_tx_o 
on highest bit
+   wire [31:0] debug_rx_1 = 
{uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV,
                             irq,
                             GMII_RXD,
                             GMII_TXD};
-   //assign      debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] };
-
-   assign      debug = master_time;
-   assign      debug_clk[0] = wb_clk;
-   assign      debug_clk[1] = dsp_clk; 
-
-   assign      debug_gpio_0 = 32'd0;
-   //assign      debug_gpio_1 = debug_rx_1;
-   assign      debug_gpio_1 = {exp_pps_in, exp_pps_out, pps_in, pps_int};
    
+   wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] };
+   
+   wire [31:0] debug_time =  {uart_tx_o, 7'b0,
+                             irq,
+                             6'b0, GMII_RX_DV, GMII_TX_EN,
+                             4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int};
+   
+   // Choose actual debug buses
+   assign        debug = master_time;
+   assign        debug_clk[0] = wb_clk;
+   assign        debug_clk[1] = dsp_clk;       
+   assign        debug_gpio_0 = 32'd0;  // Not used b/c of ATR
+   assign        debug_gpio_1 = debug_time;
+   
 endmodule // u2_basic

Modified: usrp2/trunk/fpga/top/u2_fpga/u2_fpga.ise
===================================================================
(Binary files differ)