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[Commit-gnuradio] r7424 - usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx
From: |
matt |
Subject: |
[Commit-gnuradio] r7424 - usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx |
Date: |
Sun, 13 Jan 2008 18:52:46 -0700 (MST) |
Author: matt
Date: 2008-01-13 18:52:46 -0700 (Sun, 13 Jan 2008)
New Revision: 7424
Modified:
usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_FF.v
Log:
make ISE happy
Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_FF.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_FF.v 2008-01-14 01:35:33 UTC
(rev 7423)
+++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_FF.v 2008-01-14 01:52:46 UTC
(rev 7424)
@@ -67,17 +67,17 @@
input Clk_MAC ,
input Clk_SYS ,
//MAC_tx_ctrl
- output [7:0] Fifo_data ,
+ output reg [7:0]Fifo_data ,
input Fifo_rd ,
input Fifo_rd_finish ,
input Fifo_rd_retry ,
- output Fifo_eop ,
- output Fifo_da ,
- output Fifo_ra ,
- output Fifo_data_err_empty ,
+ output reg Fifo_eop ,
+ output reg Fifo_da ,
+ output reg Fifo_ra ,
+ output reg Fifo_data_err_empty ,
output Fifo_data_err_full ,
//user interface
- output Tx_mac_wa ,
+ output reg Tx_mac_wa ,
input Tx_mac_wr ,
input [31:0] Tx_mac_data ,
input [1:0] Tx_mac_BE ,//big endian
@@ -145,15 +145,12 @@
reg [35:0] Dout_reg;
reg Packet_number_sub_edge;
reg Packet_number_add;
-reg Fifo_ra;
-reg Fifo_data_err_empty;
reg [5:0] Packet_number_inFF;
reg [5:0] Packet_number_inFF_reg;
reg Dout_reg_en;
reg Add_rd_add;
-reg Tx_mac_wa ;
reg Tx_mac_wr_dl1 ;
reg [31:0] Tx_mac_data_dl1 ;
reg [1:0] Tx_mac_BE_dl1 ;
@@ -165,9 +162,6 @@
reg Packet_number_sub_dl1 ;
reg Packet_number_sub_dl2 ;
reg [4:0] Fifo_data_count ;
-reg [7:0] Fifo_data ;
-reg Fifo_da ;
-reg Fifo_eop ;
reg Fifo_ra_tmp ;
reg Pkt_sub_apply_tmp ;
reg Pkt_sub_apply ;
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