[Commit-gnuradio] r7431 - usrp2/trunk/fpga/sdr_lib

[matt]

Author: matt
Date: 2008-01-14 00:09:28 -0700 (Mon, 14 Jan 2008)
New Revision: 7431

Modified:
   usrp2/trunk/fpga/sdr_lib/hb_decim.v
   usrp2/trunk/fpga/sdr_lib/hb_tb.v
Log:
work in progress


Modified: usrp2/trunk/fpga/sdr_lib/hb_decim.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/hb_decim.v 2008-01-14 07:06:40 UTC (rev 7430)
+++ usrp2/trunk/fpga/sdr_lib/hb_decim.v 2008-01-14 07:09:28 UTC (rev 7431)
@@ -5,17 +5,17 @@
 module hb_decim
   #(parameter SWIDTH = 17,
     parameter CWIDTH = 18,
-    parameter TWIDTH = 16,
+    parameter TWIDTH = 20,
     parameter ACC_WIDTH = 40)
     (input clk, input rst,
      input set_stb, input [7:0] set_addr, input [31:0] set_data,
      input [SWIDTH-1:0] sample_in,
      input strobe_in,
-     output [SWIDTH-1:0] sample_out,
+     output reg [SWIDTH:0] sample_out,
      output strobe_out 
      );
 
-   reg [3:0] even_addr, odd_addr_a, odd_addr_b, coeff_addr;
+   wire [3:0] even_addr, odd_addr_a, odd_addr_b, coeff_addr;
    genvar    i;
    
    wire [SWIDTH-1:0] cascade, even_sample, odd_sample_a, odd_sample_b;
@@ -28,10 +28,30 @@
 
    wire [TWIDTH-1:0] control_word;
    reg [3:0]        phase;
+   reg                      write_phase;
    wire             write_even, write_odd;
    wire             signed [35:0]           product;
    reg                      signed [ACC_WIDTH-1:0] accum;
-   wire             clear_accum = 0;
+   wire             load_accum, do_accum;
+
+   always @(posedge clk)
+     if(rst)
+       write_phase <= 0;
+     else if(strobe_in)
+       write_phase <= ~write_phase;
+
+   assign           write_even = strobe_in & write_phase;
+   assign           write_odd = strobe_in & ~write_phase;
+
+   // Parse control word
+   assign           coeff_addr = control_word[3:0];
+   assign           odd_addr_b = control_word[7:4];
+   assign           odd_addr_a = control_word[11:8];
+   assign           even_addr = control_word[15:12];
+   assign           done = control_word[16];
+   assign           load_accum = control_word[17];
+   assign           do_accum = control_word[18];            
+   assign           strobe_out = control_word[19];
    
    generate
       for (i=0;i<TWIDTH;i=i+1)
@@ -65,7 +85,7 @@
                        
.A0(odd_addr_a[0]),.A1(odd_addr_a[1]),.A2(odd_addr_a[2]),.A3(odd_addr_a[3]),
                        .CE(write_odd),.CLK(clk),.D(sample_in[i]));
           SRL16E
-            srl_odd_b(.Q(even_sample[i]),
+            srl_odd_b(.Q(odd_sample_b[i]),
                       
.A0(odd_addr_b[0]),.A1(odd_addr_b[1]),.A2(odd_addr_b[2]),.A3(odd_addr_b[3]),
                       .CE(write_odd),.CLK(clk),.D(cascade[i]));
        end
@@ -75,16 +95,37 @@
    always @(posedge clk)
      if(rst)
        phase <= 0;
-
+     else if(strobe_in & ~write_phase)
+       phase <= 1;
+     else if(done)
+       phase <= 0;
+     else if(phase != 0)
+       phase <= phase + 1;
+   
    MULT18X18S mult(.P(product),.A(odd_coeff),.B(odd_sum),.C(clk),.CE(1),.R(0));
 
+   reg do_accum_d1, strobe_out_d1, strobe_out_d2;
+   
+   always @(posedge clk) do_accum_d1 <= do_accum;
+   always @(posedge clk) strobe_out_d1 <= strobe_out;
+   always @(posedge clk) strobe_out_d2 <= strobe_out_d1;
+
+   reg [SWIDTH-1:0] even_sample_d1;
    always @(posedge clk)
+     if(write_even)
+       even_sample_d1 <= even_sample;
+   
+   always @(posedge clk)
      if(rst)
        accum <= 0;
-     else if(clear_accum)
-       accum <= 0;
-     else
+     else if(load_accum)
+       accum <= product + (even_sample_d1 << 15);
+     else if(do_accum_d1)
        accum <= accum + product;
 
+   always @(posedge clk)
+     if(strobe_out_d2)
+       sample_out <= accum; // + even_sample;
+
 endmodule // hb_decim
 

Modified: usrp2/trunk/fpga/sdr_lib/hb_tb.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/hb_tb.v    2008-01-14 07:06:40 UTC (rev 7430)
+++ usrp2/trunk/fpga/sdr_lib/hb_tb.v    2008-01-14 07:09:28 UTC (rev 7431)
@@ -3,19 +3,19 @@
 
    localparam SWIDTH = 17;
    localparam CWIDTH = 18;
-   localparam TWIDTH = 16;
+   localparam TWIDTH = 20;
    localparam ACC_WIDTH = 40;
    
    reg clk = 0, rst = 1;
    wire strobe_in, strobe_out;
    reg [SWIDTH-1:0] sample_in;
-   wire [SWIDTH-1:0] sample_out;
+   wire signed [SWIDTH:0] sample_out;
 
    reg                set_stb;
    reg [7:0]   set_addr;
    reg [31:0]  set_data;
 
-   localparam  DECIM = 15;
+   localparam  DECIM = 3;
    
    initial $dumpfile("hb_tb.vcd");
    initial $dumpvars(0,hb_tb);
@@ -42,12 +42,114 @@
    hb_decim #(.SWIDTH(SWIDTH),.CWIDTH(CWIDTH),
              .TWIDTH(TWIDTH),.ACC_WIDTH(ACC_WIDTH)) hb_decim
      (.clk(clk), .rst(rst),
-      .set_stb(set_stb), .set_addr(), .set_data(),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
       .sample_in(sample_in),
       .strobe_in(strobe_in),
       .sample_out(sample_out),
       .strobe_out(strobe_out)
       );
 
+   initial
+     begin : load_coeffs
+       @(negedge rst);
+       @(posedge clk);
+       set_addr <= 124;   // load coeffs
+       set_stb <= 1;
+       set_data <= -18'd49;
+       @(posedge clk);
+       set_data <= 18'd165;
+       @(posedge clk);
+       set_data <= -18'd412;
+       @(posedge clk);
+       set_data <= 18'd873;
+       @(posedge clk);
+       set_data <= -18'd1681;
+       @(posedge clk);
+       set_data <= 18'd3135;
+       @(posedge clk);
+       set_data <= -18'd6282;
+       @(posedge clk);
+       set_data <= 18'd20628;
+       @(posedge clk);
+       set_addr <=125;  // load table
+       // { stb_out, accum, load_accum, done, even_addr, odd_addr_a, 
odd_addr_b, coeff_addr }
+       set_data <= {1'b1,1'b1,1'b0,1'b1,4'd15,4'd15,4'd0,4'd0}; // Phase 8
+       @(posedge clk);
+       set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd14,4'd1,4'd1}; // Phase 7
+       @(posedge clk);
+       set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd13,4'd2,4'd2}; // Phase 6
+       @(posedge clk);
+       set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd12,4'd3,4'd3}; // Phase 5
+       @(posedge clk);
+       set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd11,4'd4,4'd4}; // Phase 4
+       @(posedge clk);
+       set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd10,4'd5,4'd5}; // Phase 3
+       @(posedge clk);
+       set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd9,4'd6,4'd6};  // Phase 2
+       @(posedge clk);
+       set_data <= {1'b0,1'b0,1'b1,1'b0,4'd15,4'd8,4'd7,4'd7};   // Phase 1
+       @(posedge clk);
+       set_data <= {1'b0,1'b0,1'b0,1'b0,4'd15,4'd8,4'd7,4'd7};   // Phase 0
+       @(posedge clk);
+       set_stb <= 0;
+     end // block: load_coeffs
    
+   initial
+     begin
+       sample_in <= 0;
+       repeat(40)
+         @(posedge strobe_in);
+       $display("EVEN");
+       sample_in <= 0;
+       repeat(10)
+         @(posedge strobe_in);
+       sample_in <= 1;
+       @(posedge strobe_in);
+       sample_in <= 0;
+       repeat(40)
+         @(posedge strobe_in);
+       sample_in <= 1;
+       repeat(40)
+         @(posedge strobe_in);
+       sample_in <= 0;
+       repeat(60)
+         @(posedge strobe_in);
+       sample_in <= 1;
+       repeat(2)
+         @(posedge strobe_in);
+       sample_in <= 0;
+       repeat(60)
+         @(posedge strobe_in);
+       $display("ODD");
+       sample_in <= 0;
+       repeat(10)
+         @(posedge strobe_in);
+       sample_in <= 1;
+       @(posedge strobe_in);
+       sample_in <= 0;
+       repeat(40)
+         @(posedge strobe_in);
+       sample_in <= 1;
+       repeat(40)
+         @(posedge strobe_in);
+       sample_in <= 0;
+       repeat(60)
+         @(posedge strobe_in);
+       sample_in <= 1;
+       repeat(2)
+         @(posedge strobe_in);
+       sample_in <= 0;
+       repeat(60)
+         @(posedge strobe_in);
+       $finish;
+     end
+
+   always @(posedge clk)
+     if(strobe_in)
+       $display(sample_in);
+   
+      always @(posedge clk)
+       if(strobe_out)
+         $display("\t",sample_out);
+
 endmodule // hb_tb