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[Commit-gnuradio] r7433 - usrp2/trunk/fpga/eth/rtl/verilog
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From: |
matt |
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Subject: |
[Commit-gnuradio] r7433 - usrp2/trunk/fpga/eth/rtl/verilog |
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Date: |
Mon, 14 Jan 2008 00:39:47 -0700 (MST) |
Author: matt
Date: 2008-01-14 00:39:47 -0700 (Mon, 14 Jan 2008)
New Revision: 7433
Modified:
usrp2/trunk/fpga/eth/rtl/verilog/RMON.v
Log:
minor changes, but a lot of reformatting for my sanity
Modified: usrp2/trunk/fpga/eth/rtl/verilog/RMON.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/RMON.v 2008-01-14 07:11:20 UTC (rev
7432)
+++ usrp2/trunk/fpga/eth/rtl/verilog/RMON.v 2008-01-14 07:39:47 UTC (rev
7433)
@@ -53,130 +53,111 @@
// no message
//
-module RMON (
-Clk ,
-Reset ,
-//Tx_RMON
-Tx_pkt_type_rmon ,
-Tx_pkt_length_rmon ,
-Tx_apply_rmon ,
-Tx_pkt_err_type_rmon,
-//Tx_RMON
-Rx_pkt_type_rmon ,
-Rx_pkt_length_rmon ,
-Rx_apply_rmon ,
-Rx_pkt_err_type_rmon,
-//CPU
-CPU_rd_addr ,
-CPU_rd_apply ,
-CPU_rd_grant ,
-CPU_rd_dout
+module RMON
+ (input Clk ,
+ input Reset ,
+ //Tx_RMON
+ input [2:0] Tx_pkt_type_rmon ,
+ input [15:0] Tx_pkt_length_rmon ,
+ input Tx_apply_rmon ,
+ input [2:0] Tx_pkt_err_type_rmon,
+ //Tx_RMON
+ input [2:0] Rx_pkt_type_rmon ,
+ input [15:0] Rx_pkt_length_rmon ,
+ input Rx_apply_rmon ,
+ input [2:0] Rx_pkt_err_type_rmon,
+ //CPU
+ input [5:0] CPU_rd_addr ,
+ input CPU_rd_apply ,
+ output CPU_rd_grant ,
+ output [31:0] CPU_rd_dout
+ );
+
+ //
******************************************************************************
+ // interface signals
+ //
******************************************************************************
+ wire Reg_apply_0 ;
+ wire [4:0] Reg_addr_0 ;
+ wire [15:0] Reg_data_0 ;
+ wire Reg_next_0 ;
+ wire Reg_apply_1 ;
+ wire [4:0] Reg_addr_1 ;
+ wire [15:0] Reg_data_1 ;
+ wire Reg_next_1 ;
+ wire [5:0] Addra ;
+ wire [31:0] Dina ;
+ reg [31:0] Douta ;
+ wire Wea ;
-);
-input Clk ;
-input Reset ;
- //Tx_RMON
-input [2:0] Tx_pkt_type_rmon ;
-input [15:0] Tx_pkt_length_rmon ;
-input Tx_apply_rmon ;
-input [2:0] Tx_pkt_err_type_rmon;
- //Tx_RMON
-input [2:0] Rx_pkt_type_rmon ;
-input [15:0] Rx_pkt_length_rmon ;
-input Rx_apply_rmon ;
-input [2:0] Rx_pkt_err_type_rmon;
- //CPU
-input [5:0] CPU_rd_addr ;
-input CPU_rd_apply ;
-output CPU_rd_grant ;
-output [31:0] CPU_rd_dout ;
-
-//******************************************************************************
-//interface signals
-//******************************************************************************
-wire Reg_apply_0 ;
-wire [4:0] Reg_addr_0 ;
-wire [15:0] Reg_data_0 ;
-wire Reg_next_0 ;
-wire Reg_apply_1 ;
-wire [4:0] Reg_addr_1 ;
-wire [15:0] Reg_data_1 ;
-wire Reg_next_1 ;
-wire [5:0] Addra ;
-wire [31:0] Dina ;
-wire [31:0] Douta ;
-wire Wea ;
-
-//******************************************************************************
-
-//assign RxAddrb=0;
-//assign TxAddrb=0;
-
-RMON_addr_gen U_0_Rx_RMON_addr_gen(
-.Clk (Clk ),
-.Reset (Reset ),
- //RMON (//RMON ),
-.Pkt_type_rmon (Rx_pkt_type_rmon ),
-.Pkt_length_rmon (Rx_pkt_length_rmon ),
-.Apply_rmon (Rx_apply_rmon ),
-.Pkt_err_type_rmon (Rx_pkt_err_type_rmon ),
- //Rmon_ctrl (//Rron_ctrl ),
-.Reg_apply (Reg_apply_0 ),
-.Reg_addr (Reg_addr_0 ),
-.Reg_data (Reg_data_0 ),
-.Reg_next (Reg_next_0 ),
- //CPU (//CPU ),
-.Reg_drop_apply ( ));
-
-RMON_addr_gen U_0_Tx_RMON_addr_gen(
-.Clk (Clk ),
-.Reset (Reset ),
- //RMON (//RMON ),
-.Pkt_type_rmon (Tx_pkt_type_rmon ),
-.Pkt_length_rmon (Tx_pkt_length_rmon ),
-.Apply_rmon (Tx_apply_rmon ),
-.Pkt_err_type_rmon (Tx_pkt_err_type_rmon ),
- //Rmon_ctrl (//Rron_ctrl ),
-.Reg_apply (Reg_apply_1 ),
-.Reg_addr (Reg_addr_1 ),
-.Reg_data (Reg_data_1 ),
-.Reg_next (Reg_next_1 ),
- //CPU (//CPU ),
-.Reg_drop_apply ( ));
-
-RMON_ctrl U_RMON_ctrl(
-.Clk (Clk ),
-.Reset (Reset ),
- //RMON_ctrl (//RMON_ctrl ),
-.Reg_apply_0 (Reg_apply_0 ),
-.Reg_addr_0 (Reg_addr_0 ),
-.Reg_data_0 (Reg_data_0 ),
-.Reg_next_0 (Reg_next_0 ),
-.Reg_apply_1 (Reg_apply_1 ),
-.Reg_addr_1 (Reg_addr_1 ),
-.Reg_data_1 (Reg_data_1 ),
-.Reg_next_1 (Reg_next_1 ),
- //dual-port ram (//dual-port ram ),
-.Addra (Addra ),
-.Dina (Dina ),
-.Douta (Douta ),
-.Wea (Wea ),
- //CPU (//CPU ),
-.CPU_rd_addr (CPU_rd_addr ),
-.CPU_rd_apply (CPU_rd_apply ),
-.CPU_rd_grant (CPU_rd_grant ),
-.CPU_rd_dout (CPU_rd_dout )
-);
+ //
******************************************************************************
- reg [31:0] RMON_ram [0:63];
- reg [31:0] Douta_reg;
+ RMON_addr_gen U_0_Rx_RMON_addr_gen
+ (.Clk (Clk ),
+ .Reset (Reset ),
+ //RMON
+ .Pkt_type_rmon (Rx_pkt_type_rmon ),
+ .Pkt_length_rmon (Rx_pkt_length_rmon ),
+ .Apply_rmon (Rx_apply_rmon ),
+ .Pkt_err_type_rmon (Rx_pkt_err_type_rmon ),
+ //Rmon_ctrl
+ .Reg_apply (Reg_apply_0 ),
+ .Reg_addr (Reg_addr_0 ),
+ .Reg_data (Reg_data_0 ),
+ .Reg_next (Reg_next_0 ),
+ //CPU
+ .Reg_drop_apply ( ) );
+
+ RMON_addr_gen U_0_Tx_RMON_addr_gen
+ (.Clk (Clk ),
+ .Reset (Reset ),
+ //RMON
+ .Pkt_type_rmon (Tx_pkt_type_rmon ),
+ .Pkt_length_rmon (Tx_pkt_length_rmon ),
+ .Apply_rmon (Tx_apply_rmon ),
+ .Pkt_err_type_rmon (Tx_pkt_err_type_rmon ),
+ //Rmon_ctrl
+ .Reg_apply (Reg_apply_1 ),
+ .Reg_addr (Reg_addr_1 ),
+ .Reg_data (Reg_data_1 ),
+ .Reg_next (Reg_next_1 ),
+ //CPU
+ .Reg_drop_apply ( ) );
+
+ RMON_ctrl U_RMON_ctrl
+ (.Clk (Clk ),
+ .Reset (Reset ),
+ //RMON_ctrl
+ .Reg_apply_0 (Reg_apply_0 ),
+ .Reg_addr_0 (Reg_addr_0 ),
+ .Reg_data_0 (Reg_data_0 ),
+ .Reg_next_0 (Reg_next_0 ),
+ .Reg_apply_1 (Reg_apply_1 ),
+ .Reg_addr_1 (Reg_addr_1 ),
+ .Reg_data_1 (Reg_data_1 ),
+ .Reg_next_1 (Reg_next_1 ),
+ //dual-port ram
+ .Addra (Addra ),
+ .Dina (Dina ),
+ .Douta (Douta ),
+ .Wea (Wea ),
+ //CPU
+ .CPU_rd_addr (CPU_rd_addr ),
+ .CPU_rd_apply (CPU_rd_apply ),
+ .CPU_rd_grant (CPU_rd_grant ),
+ .CPU_rd_dout (CPU_rd_dout ) );
+
+ reg [31:0] RMON_ram [0:63];
+ wire [31:0] Douta_imm = RMON_ram[Addra];
+ integer i;
+ initial
+ for(i=0;i<64;i=i+1)
+ RMON_ram[i] = 32'd0;
+
always @(posedge Clk)
if(Wea)
RMON_ram[Addra] <= Dina;
- //assign Douta = RMON_ram[Addra];
+
always @(posedge Clk)
- Douta_reg <= RMON_ram[Addra];
- assign Douta = Douta_reg;
+ Douta <= Douta_imm;
endmodule // RMON
-
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