[Commit-gnuradio] r7481 - in usrp2/trunk/fpga/opencores/aemb/rtl/verilog: . CVS

[matt]

Author: matt
Date: 2008-01-20 13:15:14 -0700 (Sun, 20 Jan 2008)
New Revision: 7481

Modified:
   usrp2/trunk/fpga/opencores/aemb/rtl/verilog/CVS/Entries
   usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_edk32.v
   usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v
Log:
shawn renamed the signals in my fix of the barrel shifter stall


Modified: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/CVS/Entries
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/rtl/verilog/CVS/Entries     2008-01-20 
19:50:29 UTC (rev 7480)
+++ usrp2/trunk/fpga/opencores/aemb/rtl/verilog/CVS/Entries     2008-01-20 
20:15:14 UTC (rev 7481)
@@ -1,5 +1,3 @@
-/aeMB_edk32.v/1.13/Tue Jan  8 19:38:58 2008//
-/aeMB_ibuf.v/1.8/Tue Jan  8 19:38:58 2008//
 /aeMB_sim.v/1.1/Tue Jan  8 19:38:59 2008//
 /aeMB2_aslu.v/1.9/Mon Jan 14 07:10:14 2008//
 /aeMB2_bpcu.v/1.5/Tue Jan  8 19:42:05 2008//
@@ -15,4 +13,6 @@
 /aeMB_ctrl.v/1.10/Tue Jan  8 19:42:05 2008//
 /aeMB_regf.v/1.3/Tue Jan  8 19:42:06 2008//
 /aeMB_xecu.v/1.10/Tue Jan  8 19:42:06 2008//
+/aeMB_ibuf.v/1.9/Sun Jan 20 20:13:51 2008//
+/aeMB_edk32.v/1.14/Sun Jan 20 20:13:53 2008//
 D

Modified: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_edk32.v
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_edk32.v    2008-01-20 
19:50:29 UTC (rev 7480)
+++ usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_edk32.v    2008-01-20 
20:15:14 UTC (rev 7481)
@@ -1,4 +1,4 @@
-/* $Id: aeMB_edk32.v,v 1.13 2007/12/25 22:15:09 sybreon Exp $
+/* $Id: aeMB_edk32.v,v 1.14 2008/01/19 16:01:22 sybreon Exp $
 **
 ** AEMB EDK 3.2 Compatible Core
 ** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
@@ -32,7 +32,7 @@
    parameter DW = 32; /// Data bus address width
 
    // Optional functions
-   parameter MUL = 1; // Multiplier
+   parameter MUL = 0; // Multiplier
    parameter BSF = 1; // Barrel Shifter
    
    /*AUTOOUTPUT*/
@@ -96,7 +96,8 @@
    wire                grst = sys_rst_i;
    wire                gclk = sys_clk_i;
    wire                gena = !((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ 
fsl_ack_i) | !iwb_ack_i) & !rSTALL;   
-   wire                other_stall = (dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ 
fsl_ack_i) | ~iwb_ack_i;
+   wire                oena = ((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ 
fsl_ack_i) | !iwb_ack_i);   
+   
    // --- INSTANTIATIONS -------------------------------------
           
    aeMB_ibuf
@@ -122,8 +123,7 @@
           .gclk                        (gclk),
           .grst                        (grst),
           .gena                        (gena),
-          .other_stall                 (other_stall)
-          );   
+          .oena                        (oena));   
    
    aeMB_ctrl
      ctrl (/*AUTOINST*/
@@ -241,6 +241,9 @@
 
 /*
  $Log: aeMB_edk32.v,v $
+ Revision 1.14  2008/01/19 16:01:22  sybreon
+ Patched problem where memory access followed by dual cycle instructions were 
not stalling correctly (submitted by M. Ettus)
+
  Revision 1.13  2007/12/25 22:15:09  sybreon
  Stalls pipeline on MUL/BSF instructions results in minor speed improvements.
 
@@ -283,4 +286,4 @@
  New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
  Fixed various minor data hazard bugs.
  Code compatible with -O0/1/2/3/s generated code.
-*/ 
+*/ 
\ No newline at end of file

Modified: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v     2008-01-20 
19:50:29 UTC (rev 7480)
+++ usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v     2008-01-20 
20:15:14 UTC (rev 7481)
@@ -1,4 +1,4 @@
-/* $Id: aeMB_ibuf.v,v 1.8 2007/12/25 22:15:09 sybreon Exp $
+/* $Id: aeMB_ibuf.v,v 1.9 2008/01/19 16:01:22 sybreon Exp $
 **
 ** AEMB INSTRUCTION BUFFER
 ** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
@@ -24,7 +24,7 @@
    rIMM, rRA, rRD, rRB, rALT, rOPC, rSIMM, xIREG, rSTALL, iwb_stb_o,
    // Inputs
    rBRA, rMSR_IE, rMSR_BIP, iwb_dat_i, iwb_ack_i, sys_int_i, gclk,
-   grst, gena, other_stall
+   grst, gena, oena
    );
    // INTERNAL
    output [15:0] rIMM;
@@ -49,9 +49,8 @@
    input        sys_int_i;   
 
    // SYSTEM
-   input        gclk, grst, gena;
-   input        other_stall;
-        
+   input        gclk, grst, gena, oena;
+
    reg [15:0]   rIMM;
    reg [4:0]    rRA, rRD;
    reg [5:0]    rOPC;
@@ -145,14 +144,16 @@
        rSTALL <= 1'h0;
        // End of automatics
      end else begin
-       //rSTALL <= #1 (!rSTALL | other_stall) & (fMUL | fBSF);
-       rSTALL <= #1 (rSTALL & other_stall) | (!rSTALL & (fMUL | fBSF));
+       rSTALL <= #1 (!rSTALL & (fMUL | fBSF)) | (oena & rSTALL);       
      end
    
 endmodule // aeMB_ibuf
 
 /*
  $Log: aeMB_ibuf.v,v $
+ Revision 1.9  2008/01/19 16:01:22  sybreon
+ Patched problem where memory access followed by dual cycle instructions were 
not stalling correctly (submitted by M. Ettus)
+
  Revision 1.8  2007/12/25 22:15:09  sybreon
  Stalls pipeline on MUL/BSF instructions results in minor speed improvements.
 
@@ -180,4 +181,4 @@
  New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
  Fixed various minor data hazard bugs.
  Code compatible with -O0/1/2/3/s generated code.
-*/
+*/
\ No newline at end of file