[Commit-gnuradio] r8133 - usrp2/trunk/fpga/sdr_lib

[matt]

Author: matt
Date: 2008-03-28 16:20:36 -0600 (Fri, 28 Mar 2008)
New Revision: 8133

Modified:
   usrp2/trunk/fpga/sdr_lib/hb_dec.v
Log:
progress


Modified: usrp2/trunk/fpga/sdr_lib/hb_dec.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/hb_dec.v   2008-03-28 22:20:01 UTC (rev 8132)
+++ usrp2/trunk/fpga/sdr_lib/hb_dec.v   2008-03-28 22:20:36 UTC (rev 8133)
@@ -13,7 +13,7 @@
      output reg stb_out,
      output [WIDTH-1:0] data_out);
 
-   wire [3:0]          addr_odd_a, addr_odd_b, addr_odd_c, addr_odd_d, 
addr_even;
+   reg [3:0]           addr_odd_a, addr_odd_b, addr_odd_c, addr_odd_d, 
addr_even;
    wire [WIDTH-1:0]    data_odd_a, data_odd_b, data_odd_c, data_odd_d, 
data_even;
    wire [WIDTH-1:0]    sum1, sum2;     
    reg [WIDTH-1:0]     final_sum;
@@ -21,23 +21,85 @@
 
    wire [2:0]          coeff_addr;
    wire [35:0]                 prod1, prod2;
+
+   wire                write_odd, write_even;
+   reg                         odd_even;
+   reg [2:0]           phase;
    
+   always @(posedge clk)
+     if(rst)
+       odd_even <= 0;
+     else if(stb_in)
+       odd_even <= ~odd_even;
+
+   assign              write_odd = stb_in & odd_even;
+   assign              write_even = stb_in & ~odd_even;
+
+   always @(posedge clk)
+     if(rst)
+       phase <= 0;
+     else if(stb_in & odd_even)
+       phase <= 1;
+     else if(phase == 4)
+       phase <= 0;
+     else if(phase != 0)
+       phase <= phase + 1;
+
+   assign              coeff_addr = phase;
+
    always @*
+     case(phase)
+       1 : addr_odd_a = 1;
+       2 : addr_odd_a = 7;
+       3 : addr_odd_a = 9;
+       4 : addr_odd_a = 15;
+       default : addr_odd_a = 3;
+     endcase // case(phase)
+   
+   always @*
+     case(phase)
+       1 : addr_odd_b = 1;
+       2 : addr_odd_b = 7;
+       3 : addr_odd_b = 9;
+       4 : addr_odd_b = 15;
+       default : addr_odd_b = 3;
+     endcase // case(phase)
+   
+   always @*
+     case(phase)
+       1 : addr_odd_c = 4;
+       2 : addr_odd_c = 5;
+       3 : addr_odd_c = 6;
+       4 : addr_odd_c = 15;
+       default : addr_odd_c = 3;
+     endcase // case(phase)
+   
+   always @*
+     case(phase)
+       1 : addr_odd_d = 2;
+       2 : addr_odd_d = 3;
+       3 : addr_odd_d = 5;
+       4 : addr_odd_d = 5;
+       default : addr_odd_d = 3;
+     endcase // case(phase)
+   
+   always @*
      case(coeff_addr)
-       0 : coeff1 <= 12345;
-       1 : coeff1 <= 1235;
-       2 : coeff1 <= 3456;
-       3 : coeff1 <= 345;
-       default : coeff1 <= 23456;
+       0 : coeff1 = 12345;
+       1 : coeff1 = 1235;
+       2 : coeff1 = 3456;
+       3 : coeff1 = 345;
+       3 : coeff1 = 345;
+       default : coeff1 = 23456;
      endcase // case(coeff_addr)
    
    always @*
      case(coeff_addr)
-       0 : coeff2 <= 12345;
-       1 : coeff2 <= 1235;
-       2 : coeff2 <= 3456;
-       3 : coeff2 <= 345;
-       default : coeff2 <= 23456;
+       0 : coeff2 = 12345;
+       1 : coeff2 = 12;
+       2 : coeff2 = 356;
+       3 : coeff2 = 45;
+       default : coeff2 = 23456;
      endcase // case(coeff_addr)
    
    srl #(.WIDTH(18)) srl_odd_a