[Commit-gnuradio] r8166 - in gnuradio/branches/developers/gnychis/fpga/usrp/fpga: inband_lib toplevel/usrp_inband_usb

[gnychis]

Author: gnychis
Date: 2008-04-09 13:48:35 -0600 (Wed, 09 Apr 2008)
New Revision: 8166

Modified:
   gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/register_io.v
   
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
Log:
removing read back of registers, needs to be tested still

Modified: 
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/register_io.v
===================================================================
--- 
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/register_io.v    
    2008-04-09 19:08:43 UTC (rev 8165)
+++ 
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/register_io.v    
    2008-04-09 19:48:35 UTC (rev 8166)
@@ -1,10 +1,7 @@
 module register_io
        (clk, reset, enable, addr, datain, dataout, debugbus, addr_wr, data_wr, 
strobe_wr,
         rssi_0, rssi_1, rssi_2, rssi_3, threshhold, rssi_wait, reg_0, reg_1, 
reg_2, reg_3, 
-     atr_tx_delay, atr_rx_delay, master_controls, debug_en, interp_rate, 
decim_rate, 
-     atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1, 
atr_rxval_1,
-     atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3, 
atr_rxval_3, 
-     txa_refclk, txb_refclk, rxa_refclk, rxb_refclk, misc, txmux);   
+     debug_en, misc, txmux);   
        
        input clk;
        input reset;
@@ -26,77 +23,10 @@
        input wire [15:0] reg_1; 
        input wire [15:0] reg_2; 
        input wire [15:0] reg_3;
-       input wire [11:0] atr_tx_delay;
-       input wire [11:0] atr_rx_delay;
-       input wire [7:0]  master_controls;
        input wire [3:0]  debug_en;
-       input wire [15:0] atr_mask_0;
-       input wire [15:0] atr_txval_0;
-       input wire [15:0] atr_rxval_0;
-       input wire [15:0] atr_mask_1;
-       input wire [15:0] atr_txval_1;
-       input wire [15:0] atr_rxval_1;
-       input wire [15:0] atr_mask_2;
-       input wire [15:0] atr_txval_2;
-       input wire [15:0] atr_rxval_2;
-       input wire [15:0] atr_mask_3;
-       input wire [15:0] atr_txval_3;
-       input wire [15:0] atr_rxval_3;
-       input wire [7:0]  txa_refclk;
-       input wire [7:0]  txb_refclk;
-       input wire [7:0]  rxa_refclk;
-       input wire [7:0]  rxb_refclk;
-       input wire [7:0]  interp_rate;
-       input wire [7:0]  decim_rate;
        input wire [7:0]  misc;
        input wire [31:0] txmux;
        
-       wire [31:0] bundle[43:0]; 
-   assign bundle[0] = 32'hFFFFFFFF;
-   assign bundle[1] = 32'hFFFFFFFF;
-   assign bundle[2] = {20'd0, atr_tx_delay};
-   assign bundle[3] = {20'd0, atr_rx_delay};
-   assign bundle[4] = {24'sd0, master_controls};
-   assign bundle[5] = 32'hFFFFFFFF;
-   assign bundle[6] = 32'hFFFFFFFF;
-   assign bundle[7] = 32'hFFFFFFFF;
-   assign bundle[8] = 32'hFFFFFFFF;
-   assign bundle[9] = {15'd0, reg_0};
-   assign bundle[10] = {15'd0, reg_1};
-   assign bundle[11] = {15'd0, reg_2};
-   assign bundle[12] = {15'd0, reg_3};
-   assign bundle[13] = {15'd0, misc};
-   assign bundle[14] = {28'd0, debug_en};
-   assign bundle[15] = 32'hFFFFFFFF;
-   assign bundle[16] = 32'hFFFFFFFF;
-   assign bundle[17] = 32'hFFFFFFFF;
-   assign bundle[18] = 32'hFFFFFFFF;
-   assign bundle[19] = 32'hFFFFFFFF;
-   assign bundle[20] = {16'd0, atr_mask_0};
-   assign bundle[21] = {16'd0, atr_txval_0};
-   assign bundle[22] = {16'd0, atr_rxval_0};
-   assign bundle[23] = {16'd0, atr_mask_1};
-   assign bundle[24] = {16'd0, atr_txval_1};
-   assign bundle[25] = {16'd0, atr_rxval_1};
-   assign bundle[26] = {16'd0, atr_mask_2};
-   assign bundle[27] = {16'd0, atr_txval_2};
-   assign bundle[28] = {16'd0, atr_rxval_2};
-   assign bundle[29] = {16'd0, atr_mask_3};
-   assign bundle[30] = {16'd0, atr_txval_3};
-   assign bundle[31] = {16'd0, atr_rxval_3};
-   assign bundle[32] = {24'd0, interp_rate};
-   assign bundle[33] = {24'd0, decim_rate};
-   assign bundle[34] = 32'hFFFFFFFF;
-   assign bundle[35] = 32'hFFFFFFFF;
-   assign bundle[36] = 32'hFFFFFFFF;
-   assign bundle[37] = 32'hFFFFFFFF;
-   assign bundle[38] = 32'hFFFFFFFF;
-   assign bundle[39] = txmux;
-   assign bundle[40] = {24'd0, txa_refclk};
-   assign bundle[41] = {24'd0, rxa_refclk};
-   assign bundle[42] = {24'd0, txb_refclk};
-   assign bundle[43] = {24'd0, rxb_refclk};  
-
        reg strobe;
        wire [31:0] out[2:1];
        assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]};

Modified: 
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
===================================================================
--- 
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
      2008-04-09 19:08:43 UTC (rev 8165)
+++ 
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
      2008-04-09 19:48:35 UTC (rev 8166)
@@ -377,42 +377,14 @@
    //assign serial_data = data_wr;
    //assign serial_addr = addr_wr;
 
-   //wires for register connection
-       wire [11:0] atr_tx_delay;
-       wire [11:0] atr_rx_delay;
-       wire [7:0]  master_controls;
-       wire [3:0]  debug_en;
-       wire [15:0] atr_mask_0;
-       wire [15:0] atr_txval_0;
-       wire [15:0] atr_rxval_0;
-       wire [15:0] atr_mask_1;
-       wire [15:0] atr_txval_1;
-       wire [15:0] atr_rxval_1;
-       wire [15:0] atr_mask_2;
-       wire [15:0] atr_txval_2;
-       wire [15:0] atr_rxval_2;
-       wire [15:0] atr_mask_3;
-       wire [15:0] atr_txval_3;
-       wire [15:0] atr_rxval_3;
-       wire [7:0]  txa_refclk;
-       wire [7:0]  txb_refclk;
-       wire [7:0]  rxa_refclk;
-       wire [7:0]  rxb_refclk; 
-        
    register_io register_control
     
(.clk(clk64),.reset(1'b0),.enable(reg_io_enable),.addr(reg_addr),.datain(reg_data_in),
-     .dataout(reg_data_out), .data_wr(data_wr), .addr_wr(addr_wr), 
.strobe_wr(strobe_wr),
+     .dataout(reg_data_out), .addr_wr(addr_wr), .data_wr(data_wr), 
.strobe_wr(strobe_wr),
      .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), 
      .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
         .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
-     .interp_rate(interp_rate), .decim_rate(decim_rate), .misc(settings), 
-        .txmux({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}), 
-        .atr_tx_delay(atr_tx_delay), .atr_rx_delay(atr_rx_delay), 
.master_controls(master_controls), 
-        .debug_en(debug_en), .atr_mask_0(atr_mask_0), 
.atr_txval_0(atr_txval_0), .atr_rxval_0(atr_rxval_0),
-        .atr_mask_1(atr_mask_1), .atr_txval_1(atr_txval_1), 
.atr_rxval_1(atr_rxval_1), 
-        .atr_mask_2(atr_mask_2), .atr_txval_2(atr_txval_2), 
.atr_rxval_2(atr_rxval_2), 
-        .atr_mask_3(atr_mask_3), .atr_txval_3(atr_txval_3), 
.atr_rxval_3(atr_rxval_3),
-        .txa_refclk(txa_refclk), .txb_refclk(txb_refclk), 
.rxa_refclk(rxa_refclk), .rxb_refclk(rxb_refclk));
+     .debug_en(debug_en), .misc(settings), 
+        .txmux({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}));
    
    
    //implementing freeze mode
@@ -437,15 +409,11 @@
        .interp_rate(interp_rate),.decim_rate(decim_rate),
        .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
        .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
-       .tx_empty(tx_empty), 
.reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
-          .atr_tx_delay(atr_tx_delay), .atr_rx_delay(atr_rx_delay), 
-          .master_controls(master_controls), .debug_en(debug_en), 
-          .atr_mask_0(atr_mask_0), .atr_txval_0(atr_txval_0), 
.atr_rxval_0(atr_rxval_0),
-          .atr_mask_1(atr_mask_1), .atr_txval_1(atr_txval_1), 
.atr_rxval_1(atr_rxval_1), 
-          .atr_mask_2(atr_mask_2), .atr_txval_2(atr_txval_2), 
.atr_rxval_2(atr_rxval_2),
-          .atr_mask_3(atr_mask_3), .atr_txval_3(atr_txval_3), 
.atr_rxval_3(atr_rxval_3), 
-          .txa_refclk(txa_refclk), .txb_refclk(txb_refclk), 
.rxa_refclk(rxa_refclk), .rxb_refclk(rxb_refclk),
-          .debug_0(tx_debugbus), .debug_1(rx_debugbus));
+       .tx_empty(tx_empty),
+       //.debug_0(rx_a_a),.debug_1(ddc0_in_i),
+       .debug_0(rx_debugbus),.debug_1(ddc0_in_i),
+       
.debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}),
+       .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
    
    io_pins io_pins
      (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b),