[Commit-gnuradio] r8173 - in gnuradio/branches/features/inband-usb/usrp/fpga: inband_lib rbf/rev2 rbf/rev4 sdr_lib toplevel/usrp_inband_usb

[gnychis]

Author: gnychis
Date: 2008-04-09 15:29:26 -0600 (Wed, 09 Apr 2008)
New Revision: 8173

Modified:
   gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/register_io.v
   gnuradio/branches/features/inband-usb/usrp/fpga/rbf/rev2/inband_1rxhb_1tx.rbf
   gnuradio/branches/features/inband-usb/usrp/fpga/rbf/rev2/inband_2rxhb_2tx.rbf
   gnuradio/branches/features/inband-usb/usrp/fpga/rbf/rev4/inband_1rxhb_1tx.rbf
   gnuradio/branches/features/inband-usb/usrp/fpga/rbf/rev4/inband_2rxhb_2tx.rbf
   gnuradio/branches/features/inband-usb/usrp/fpga/sdr_lib/master_control.v
   
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
   
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
Log:
merging -r8164:8172 from gnychis/fpga for master_control.v revert and reduced 
register read back

Modified: 
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/register_io.v
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/register_io.v    
2008-04-09 21:25:38 UTC (rev 8172)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/register_io.v    
2008-04-09 21:29:26 UTC (rev 8173)
@@ -1,10 +1,7 @@
 module register_io
        (clk, reset, enable, addr, datain, dataout, debugbus, addr_wr, data_wr, 
strobe_wr,
         rssi_0, rssi_1, rssi_2, rssi_3, threshhold, rssi_wait, reg_0, reg_1, 
reg_2, reg_3, 
-     atr_tx_delay, atr_rx_delay, master_controls, debug_en, interp_rate, 
decim_rate, 
-     atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1, 
atr_rxval_1,
-     atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3, 
atr_rxval_3, 
-     txa_refclk, txb_refclk, rxa_refclk, rxb_refclk, misc, txmux);   
+     debug_en, misc, txmux);   
        
        input clk;
        input reset;
@@ -26,77 +23,10 @@
        input wire [15:0] reg_1; 
        input wire [15:0] reg_2; 
        input wire [15:0] reg_3;
-       input wire [11:0] atr_tx_delay;
-       input wire [11:0] atr_rx_delay;
-       input wire [7:0]  master_controls;
        input wire [3:0]  debug_en;
-       input wire [15:0] atr_mask_0;
-       input wire [15:0] atr_txval_0;
-       input wire [15:0] atr_rxval_0;
-       input wire [15:0] atr_mask_1;
-       input wire [15:0] atr_txval_1;
-       input wire [15:0] atr_rxval_1;
-       input wire [15:0] atr_mask_2;
-       input wire [15:0] atr_txval_2;
-       input wire [15:0] atr_rxval_2;
-       input wire [15:0] atr_mask_3;
-       input wire [15:0] atr_txval_3;
-       input wire [15:0] atr_rxval_3;
-       input wire [7:0]  txa_refclk;
-       input wire [7:0]  txb_refclk;
-       input wire [7:0]  rxa_refclk;
-       input wire [7:0]  rxb_refclk;
-       input wire [7:0]  interp_rate;
-       input wire [7:0]  decim_rate;
        input wire [7:0]  misc;
        input wire [31:0] txmux;
        
-       wire [31:0] bundle[43:0]; 
-   assign bundle[0] = 32'hFFFFFFFF;
-   assign bundle[1] = 32'hFFFFFFFF;
-   assign bundle[2] = {20'd0, atr_tx_delay};
-   assign bundle[3] = {20'd0, atr_rx_delay};
-   assign bundle[4] = {24'sd0, master_controls};
-   assign bundle[5] = 32'hFFFFFFFF;
-   assign bundle[6] = 32'hFFFFFFFF;
-   assign bundle[7] = 32'hFFFFFFFF;
-   assign bundle[8] = 32'hFFFFFFFF;
-   assign bundle[9] = {15'd0, reg_0};
-   assign bundle[10] = {15'd0, reg_1};
-   assign bundle[11] = {15'd0, reg_2};
-   assign bundle[12] = {15'd0, reg_3};
-   assign bundle[13] = {15'd0, misc};
-   assign bundle[14] = {28'd0, debug_en};
-   assign bundle[15] = 32'hFFFFFFFF;
-   assign bundle[16] = 32'hFFFFFFFF;
-   assign bundle[17] = 32'hFFFFFFFF;
-   assign bundle[18] = 32'hFFFFFFFF;
-   assign bundle[19] = 32'hFFFFFFFF;
-   assign bundle[20] = {16'd0, atr_mask_0};
-   assign bundle[21] = {16'd0, atr_txval_0};
-   assign bundle[22] = {16'd0, atr_rxval_0};
-   assign bundle[23] = {16'd0, atr_mask_1};
-   assign bundle[24] = {16'd0, atr_txval_1};
-   assign bundle[25] = {16'd0, atr_rxval_1};
-   assign bundle[26] = {16'd0, atr_mask_2};
-   assign bundle[27] = {16'd0, atr_txval_2};
-   assign bundle[28] = {16'd0, atr_rxval_2};
-   assign bundle[29] = {16'd0, atr_mask_3};
-   assign bundle[30] = {16'd0, atr_txval_3};
-   assign bundle[31] = {16'd0, atr_rxval_3};
-   assign bundle[32] = {24'd0, interp_rate};
-   assign bundle[33] = {24'd0, decim_rate};
-   assign bundle[34] = 32'hFFFFFFFF;
-   assign bundle[35] = 32'hFFFFFFFF;
-   assign bundle[36] = 32'hFFFFFFFF;
-   assign bundle[37] = 32'hFFFFFFFF;
-   assign bundle[38] = 32'hFFFFFFFF;
-   assign bundle[39] = txmux;
-   assign bundle[40] = {24'd0, txa_refclk};
-   assign bundle[41] = {24'd0, rxa_refclk};
-   assign bundle[42] = {24'd0, txb_refclk};
-   assign bundle[43] = {24'd0, rxb_refclk};  
-
        reg strobe;
        wire [31:0] out[2:1];
        assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]};
@@ -115,9 +45,7 @@
                 if (enable[0])
                   begin
                     //read
-                               if (addr <= 7'd43)
-                                       dataout <= bundle[addr];
-                               else if (addr <= 7'd52 && addr > 7'd50)
+                               if (addr <= 7'd52 && addr > 7'd50)
                                        dataout <= out[addr-7'd50];
                                else
                                        dataout <= 32'hFFFFFFFF;        

Modified: 
gnuradio/branches/features/inband-usb/usrp/fpga/rbf/rev2/inband_1rxhb_1tx.rbf
===================================================================
(Binary files differ)

Modified: 
gnuradio/branches/features/inband-usb/usrp/fpga/rbf/rev2/inband_2rxhb_2tx.rbf
===================================================================
(Binary files differ)

Modified: 
gnuradio/branches/features/inband-usb/usrp/fpga/rbf/rev4/inband_1rxhb_1tx.rbf
===================================================================
(Binary files differ)

Modified: 
gnuradio/branches/features/inband-usb/usrp/fpga/rbf/rev4/inband_2rxhb_2tx.rbf
===================================================================
(Binary files differ)

Modified: 
gnuradio/branches/features/inband-usb/usrp/fpga/sdr_lib/master_control.v
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/sdr_lib/master_control.v    
2008-04-09 21:25:38 UTC (rev 8172)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/sdr_lib/master_control.v    
2008-04-09 21:29:26 UTC (rev 8173)
@@ -33,20 +33,12 @@
     output rx_sample_strobe, output strobe_decim,
     input tx_empty,
     input wire [15:0] debug_0,input wire [15:0] debug_1,input wire [15:0] 
debug_2,input wire [15:0] debug_3,
-    output wire [15:0] reg_0, output wire [15:0] reg_1, output wire [15:0] 
reg_2, output wire [15:0] reg_3,
-    //the following output is for register reads only
-    output wire [11:0] atr_tx_delay, output wire [11:0] atr_rx_delay, output 
wire [7:0] master_controls,
-    output wire [3:0] debug_en, 
-    output wire [15:0] atr_mask_0, output wire [15:0] atr_txval_0, output wire 
[15:0] atr_rxval_0,
-    output wire [15:0] atr_mask_1, output wire [15:0] atr_txval_1, output wire 
[15:0] atr_rxval_1,
-    output wire [15:0] atr_mask_2, output wire [15:0] atr_txval_2, output wire 
[15:0] atr_rxval_2,
-    output wire [15:0] atr_mask_3, output wire [15:0] atr_txval_3, output wire 
[15:0] atr_rxval_3,
-    output wire [7:0] txa_refclk, output wire [7:0] txb_refclk, output wire 
[7:0] rxa_refclk, output wire [7:0] rxb_refclk
+    output wire [15:0] reg_0, output wire [15:0] reg_1, output wire [15:0] 
reg_2, output wire [15:0] reg_3
     );
    
    // FIXME need a separate reset for all control settings 
    // Master Controls assignments
-   //wire [7:0] master_controls;
+   wire [7:0] master_controls;
    setting_reg #(`FR_MASTER_CTRL) 
sr_mstr_ctrl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(master_controls));
    assign     enable_tx = master_controls[0];
    assign     enable_rx = master_controls[1];
@@ -87,10 +79,9 @@
    assign tx_bus_reset = tx_reset_bus_sync2;
    assign rx_bus_reset = rx_reset_bus_sync2;
 
-   //wire [7:0]   txa_refclk, rxa_refclk, txb_refclk, rxb_refclk;
+   wire [7:0]   txa_refclk, rxa_refclk, txb_refclk, rxb_refclk;
    wire        txaclk,txbclk,rxaclk,rxbclk;
-   //wire [3:0] debug_en;
-   wire [3:0]  txcvr_ctrl;
+   wire [3:0]  debug_en, txcvr_ctrl;
 
    wire [31:0] txcvr_rxlines, txcvr_txlines;
       
@@ -123,8 +114,8 @@
 
    wire        transmit_now;
    wire        atr_ctl;
-   //wire [11:0] atr_tx_delay, atr_rx_delay;
-   //wire [15:0] atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, 
atr_txval_1, atr_rxval_1, atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, 
atr_txval_3, atr_rxval_3;
+   wire [11:0] atr_tx_delay, atr_rx_delay;
+   wire [15:0] atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1, 
atr_rxval_1, atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3, 
atr_rxval_3;
       
    setting_reg #(`FR_ATR_MASK_0) 
sr_atr_mask_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_0));
    setting_reg #(`FR_ATR_TXVAL_0) 
sr_atr_txval_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_0));

Modified: 
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
===================================================================
--- 
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
        2008-04-09 21:25:38 UTC (rev 8172)
+++ 
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
        2008-04-09 21:29:26 UTC (rev 8173)
@@ -27,7 +27,7 @@
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04  JULY 13, 
2003"
-set_global_assignment -name LAST_QUARTUS_VERSION "5.1 SP1"
+set_global_assignment -name LAST_QUARTUS_VERSION "7.2 SP2"
 
 # Pin & Location Assignments
 # ==========================
@@ -418,4 +418,6 @@
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v
 set_global_assignment -name VERILOG_FILE ../../inband_lib/channel_ram.v
-set_global_assignment -name VERILOG_FILE ../../inband_lib/register_io.v
\ No newline at end of file
+set_global_assignment -name VERILOG_FILE ../../inband_lib/register_io.v
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
\ No newline at end of file

Modified: 
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
===================================================================
--- 
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
  2008-04-09 21:25:38 UTC (rev 8172)
+++ 
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
  2008-04-09 21:29:26 UTC (rev 8173)
@@ -377,42 +377,14 @@
    //assign serial_data = data_wr;
    //assign serial_addr = addr_wr;
 
-   //wires for register connection
-       wire [11:0] atr_tx_delay;
-       wire [11:0] atr_rx_delay;
-       wire [7:0]  master_controls;
-       wire [3:0]  debug_en;
-       wire [15:0] atr_mask_0;
-       wire [15:0] atr_txval_0;
-       wire [15:0] atr_rxval_0;
-       wire [15:0] atr_mask_1;
-       wire [15:0] atr_txval_1;
-       wire [15:0] atr_rxval_1;
-       wire [15:0] atr_mask_2;
-       wire [15:0] atr_txval_2;
-       wire [15:0] atr_rxval_2;
-       wire [15:0] atr_mask_3;
-       wire [15:0] atr_txval_3;
-       wire [15:0] atr_rxval_3;
-       wire [7:0]  txa_refclk;
-       wire [7:0]  txb_refclk;
-       wire [7:0]  rxa_refclk;
-       wire [7:0]  rxb_refclk; 
-        
    register_io register_control
     
(.clk(clk64),.reset(1'b0),.enable(reg_io_enable),.addr(reg_addr),.datain(reg_data_in),
-     .dataout(reg_data_out), .data_wr(data_wr), .addr_wr(addr_wr), 
.strobe_wr(strobe_wr),
+     .dataout(reg_data_out), .addr_wr(addr_wr), .data_wr(data_wr), 
.strobe_wr(strobe_wr),
      .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), 
      .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
         .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
-     .interp_rate(interp_rate), .decim_rate(decim_rate), .misc(settings), 
-        .txmux({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}), 
-        .atr_tx_delay(atr_tx_delay), .atr_rx_delay(atr_rx_delay), 
.master_controls(master_controls), 
-        .debug_en(debug_en), .atr_mask_0(atr_mask_0), 
.atr_txval_0(atr_txval_0), .atr_rxval_0(atr_rxval_0),
-        .atr_mask_1(atr_mask_1), .atr_txval_1(atr_txval_1), 
.atr_rxval_1(atr_rxval_1), 
-        .atr_mask_2(atr_mask_2), .atr_txval_2(atr_txval_2), 
.atr_rxval_2(atr_rxval_2), 
-        .atr_mask_3(atr_mask_3), .atr_txval_3(atr_txval_3), 
.atr_rxval_3(atr_rxval_3),
-        .txa_refclk(txa_refclk), .txb_refclk(txb_refclk), 
.rxa_refclk(rxa_refclk), .rxb_refclk(rxb_refclk));
+     .debug_en(debug_en), .misc(settings), 
+        .txmux({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}));
    
    
    //implementing freeze mode
@@ -437,15 +409,11 @@
        .interp_rate(interp_rate),.decim_rate(decim_rate),
        .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
        .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
-       .tx_empty(tx_empty), 
.reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
-          .atr_tx_delay(atr_tx_delay), .atr_rx_delay(atr_rx_delay), 
-          .master_controls(master_controls), .debug_en(debug_en), 
-          .atr_mask_0(atr_mask_0), .atr_txval_0(atr_txval_0), 
.atr_rxval_0(atr_rxval_0),
-          .atr_mask_1(atr_mask_1), .atr_txval_1(atr_txval_1), 
.atr_rxval_1(atr_rxval_1), 
-          .atr_mask_2(atr_mask_2), .atr_txval_2(atr_txval_2), 
.atr_rxval_2(atr_rxval_2),
-          .atr_mask_3(atr_mask_3), .atr_txval_3(atr_txval_3), 
.atr_rxval_3(atr_rxval_3), 
-          .txa_refclk(txa_refclk), .txb_refclk(txb_refclk), 
.rxa_refclk(rxa_refclk), .rxb_refclk(rxb_refclk),
-          .debug_0(tx_debugbus), .debug_1(rx_debugbus));
+       .tx_empty(tx_empty),
+       //.debug_0(rx_a_a),.debug_1(ddc0_in_i),
+       .debug_0(rx_debugbus),.debug_1(ddc0_in_i),
+       
.debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}),
+       .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
    
    io_pins io_pins
      (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b),