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[Commit-gnuradio] r8249 - in usrp2/trunk: firmware/lib fpga/top/u2_basic
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From: |
matt |
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Subject: |
[Commit-gnuradio] r8249 - in usrp2/trunk: firmware/lib fpga/top/u2_basic |
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Date: |
Wed, 23 Apr 2008 14:07:13 -0600 (MDT) |
Author: matt
Date: 2008-04-23 14:07:11 -0600 (Wed, 23 Apr 2008)
New Revision: 8249
Modified:
usrp2/trunk/firmware/lib/memory_map.h
usrp2/trunk/fpga/top/u2_basic/u2_basic.v
Log:
Reorganized memory map to allow for more RAM, which is now parameterized,
fixed some typos in memory_map.h, widened address buses to 16 bits everywhere
Modified: usrp2/trunk/firmware/lib/memory_map.h
===================================================================
--- usrp2/trunk/firmware/lib/memory_map.h 2008-04-23 19:54:16 UTC (rev
8248)
+++ usrp2/trunk/firmware/lib/memory_map.h 2008-04-23 20:07:11 UTC (rev
8249)
@@ -16,6 +16,13 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
+/* Overall Memory Map
+ * 0000-7FFF 32K RAM space (16K on 1500, 24K on 2000, 32K on DSP)
+ * 8000-BFFF 16K Buffer Pool
+ * C000-FFFF 16K Peripherals
+ */
+
+
#ifndef INCLUDED_MEMORY_MAP_H
#define INCLUDED_MEMORY_MAP_H
@@ -44,7 +51,7 @@
// The status registers are in Slave 5, Buffer Pool Status.
// The control register is in Slave 7, Settings Bus.
-#define BUFFER_POOL_RAM_BASE 0x4000
+#define BUFFER_POOL_RAM_BASE 0x8000
#define NBUFFERS 8
#define BP_NLINES 0x0200 // number of 32-bit lines in a buffer
@@ -58,7 +65,7 @@
/////////////////////////////////////////////////////
// SPI Core, Slave 2. See core docs for more info
-#define SPI_BASE 0x8000 // Base address (16-bit)
+#define SPI_BASE 0xC000 // Base address (16-bit)
typedef struct {
volatile uint32_t txrx0;
@@ -96,7 +103,7 @@
// I2C, Slave 3
// See Wishbone I2C-Master Core Specification.
-#define I2C_BASE 0x9000
+#define I2C_BASE 0xC400
typedef struct {
volatile uint32_t prescaler_lo; // r/w
@@ -138,7 +145,7 @@
//
// These go to the daughterboard i/o pins
-#define GPIO_BASE 0xA000
+#define GPIO_BASE 0xC800
typedef struct {
volatile uint32_t io; // tx data in high 16, rx in low 16
@@ -161,7 +168,7 @@
// The status registers are in Slave 5, Buffer Pool Status.
// The control register is in Slave 7, Settings Bus.
-#define BUFFER_POOL_STATUS_BASE 0xB000
+#define BUFFER_POOL_STATUS_BASE 0xCC00
typedef struct {
volatile uint32_t last_line[NBUFFERS]; // last line xfer'd in buffer
@@ -266,7 +273,7 @@
///////////////////////////////////////////////////
// Ethernet Core, Slave 6
-#define ETH_BASE 0xC000
+#define ETH_BASE 0xD000
#include "eth_mac_regs.h"
@@ -279,14 +286,14 @@
// 1KB of address space (== 256 32-bit write-only regs)
-#define MISC_OUTPUT_BASE 0xD000
-#define TX_PROTOCOL_ENGINE_BASE 0xD080
-#define RX_PROTOCOL_ENGINE_BASE 0xD0C0
-#define BUFFER_POOL_CTRL_BASE 0xD100
-#define DSP_TX_BASE 0xD200
-#define DSP_RX_BASE 0xD280
+#define MISC_OUTPUT_BASE 0xD400
+#define TX_PROTOCOL_ENGINE_BASE 0xD480
+#define RX_PROTOCOL_ENGINE_BASE 0xD4C0
+#define BUFFER_POOL_CTRL_BASE 0xD500
+#define DSP_TX_BASE 0xD600
+#define DSP_RX_BASE 0xD680
-#define LAST_SETTING_REG 0xD3FC // last valid setting register
+#define LAST_SETTING_REG 0xD7FC // last valid setting register
// --- buffer pool control regs ---
@@ -304,7 +311,7 @@
// the buffer pool ctrl register fields
#define BPC_BUFFER(n) (((n) & 0xf) << 28)
-#define BPC_BUFFER_MASK PBC_BUFFER(~0)
+#define BPC_BUFFER_MASK BPC_BUFFER(~0)
#define BPC_BUFFER_0 BPC_BUFFER(0)
#define BPC_BUFFER_1 BPC_BUFFER(1)
#define BPC_BUFFER_2 BPC_BUFFER(2)
@@ -316,7 +323,7 @@
#define BPC_BUFFER_NIL BPC_BUFFER(0x8) // disable
#define BPC_PORT(n) (((n) & 0x7) << 25)
-#define BPC_PORT_MASK PBC_PORT(~0)
+#define BPC_PORT_MASK BPC_PORT(~0)
#define BPC_PORT_SERDES BPC_PORT(PORT_SERDES)
#define BPC_PORT_DSP BPC_PORT(PORT_DSP)
#define BPC_PORT_ETH BPC_PORT(PORT_ETH)
@@ -332,7 +339,7 @@
#define BPC_LAST_LINE(line) (((line) & 0x1ff) << 9)
#define BPC_LAST_LINE_MASK BPC_LAST_LINE(~0)
#define BPC_FIRST_LINE(line) (((line) & 0x1ff) << 0)
-#define PBC_FIRST_LINE_MASK BPC_FIRST_LINE(~0)
+#define BPC_FIRST_LINE_MASK BPC_FIRST_LINE(~0)
#define buffer_pool_ctrl ((buffer_pool_ctrl_t *) BUFFER_POOL_CTRL_BASE)
@@ -446,7 +453,7 @@
///////////////////////////////////////////////////
// Simple Programmable Interrupt Controller, Slave 8
-#define PIC_BASE 0xE000
+#define PIC_BASE 0xD800
// Interrupt request lines
// Bit numbers (LSB == 0) that correpond to interrupts into PIC
@@ -484,7 +491,7 @@
///////////////////////////////////////////////////
// Timer, Slave 9
-#define TIMER_BASE 0xE800
+#define TIMER_BASE 0xDC00
typedef struct {
volatile uint32_t time; // R: current, W: set time to interrupt
@@ -496,15 +503,29 @@
// UART, Slave 10
// include "wb16650.h" for registers
-#define UART_BASE 0xF000
+#define UART_BASE 0xE000
#define uart_regs ((wb16550_reg_t *) UART_BASE)
///////////////////////////////////////////////////
// ATR Controller, Slave 11
-#define ATR_BASE 0xF400
+#define ATR_BASE 0xE400
#define atr_regs ((int *) ATR_BASE)
+///////////////////////////////////////////////////
+ // Time Sync Controller, Slave 12
+
+#define TIMESYNC_BASE 0xE800
+
+typedef struct {
+ volatile uint32_t tick_control;
+ volatile uint32_t tick_interval;
+ volatile uint32_t delta_time;
+} timesync_regs_t;
+
+#define timesync_regs ((timesync_regs_t *) TIMESYNC_BASE)
+
#endif
+
Modified: usrp2/trunk/fpga/top/u2_basic/u2_basic.v
===================================================================
--- usrp2/trunk/fpga/top/u2_basic/u2_basic.v 2008-04-23 19:54:16 UTC (rev
8248)
+++ usrp2/trunk/fpga/top/u2_basic/u2_basic.v 2008-04-23 20:07:11 UTC (rev
8249)
@@ -3,6 +3,7 @@
//
////////////////////////////////////////////////////////////////////////////////
module u2_basic
+ #(parameter RAM_SIZE=16384)
(// Clocks
input dsp_clk,
input wb_clk,
@@ -167,11 +168,11 @@
wire
m0_rty,m1_rty,s0_rty,s1_rty,s2_rty,s3_rty,s4_rty,s5_rty,s6_rty,s7_rty,s8_rty,s9_rty,s10_rty,s11_rty,s12_rty;
wire
m0_we,m1_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,s10_we,s11_we,s12_we;
- wb_1master #(.s0_addr_w(2),.s0_addr(2'b00),.s1_addr_w(2),.s1_addr(2'b01),
-
.s215_addr_w(6),.s2_addr(6'b100000),.s3_addr(6'b100100),.s4_addr(6'b101000),
-
.s5_addr(6'b101100),.s6_addr(6'b110000),.s7_addr(6'b110100),.s8_addr(6'b111000),
-
.s9_addr(6'b111010),.s10_addr(6'b111100),.s11_addr(6'b111101),.s12_addr(6'b111110),
- .s13_addr(6'b111111),.s14_addr(6'b111111),.s15_addr(6'b111111),
+ wb_1master #(.s0_addr_w(1),.s0_addr(1'b0),.s1_addr_w(2),.s1_addr(2'b10),
+
.s215_addr_w(6),.s2_addr(6'b1100_00),.s3_addr(6'b1100_01),.s4_addr(6'b1100_10),
+
.s5_addr(6'b1100_11),.s6_addr(6'b1101_00),.s7_addr(6'b1101_01),.s8_addr(6'b1101_10),
+
.s9_addr(6'b1101_11),.s10_addr(6'b1110_00),.s11_addr(6'b1110_01),.s12_addr(6'b1110_10),
+
.s13_addr(6'b1110_11),.s14_addr(6'b1111_00),.s15_addr(6'b1111_01),
.dw(dw),.aw(aw),.sw(sw)) wb_1master
(.clk_i(wb_clk),.rst_i(wb_rst),
.m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i),
@@ -217,11 +218,11 @@
// RAM Loader
wire [31:0] ram_loader_dat, iwb_dat;
- wire [13:0] ram_loader_adr, iwb_adr;
+ wire [15:0] ram_loader_adr, iwb_adr;
wire [3:0] ram_loader_sel;
wire ram_loader_stb, ram_loader_we, ram_loader_ack;
wire iwb_ack, iwb_stb;
- ram_loader #(.AWIDTH(16))
+ ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE))
ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst),
// CPLD Interface
.cfg_clk_i(cpld_clk),
@@ -253,18 +254,18 @@
// Dual Ported RAM -- D-Port is Slave #0 on main Wishbone
// I-port connects directly to processor and ram loader
- ram_harv_cache #(.AWIDTH(14),.ICWIDTH(7),.DCWIDTH(6))
+ ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
- .ram_loader_adr_i(ram_loader_adr),
.ram_loader_dat_i(ram_loader_dat),
+ .ram_loader_adr_i(ram_loader_adr[14:0]),
.ram_loader_dat_i(ram_loader_dat),
.ram_loader_stb_i(ram_loader_stb),
.ram_loader_sel_i(ram_loader_sel),
.ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack),
.ram_loader_done_i(ram_loader_done),
- .iwb_adr_i(iwb_adr), .iwb_stb_i(iwb_stb),
+ .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb),
.iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack),
- .dwb_adr_i(s0_adr[13:0]), .dwb_dat_i(s0_dat_o),
.dwb_dat_o(s0_dat_i),
+ .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o),
.dwb_dat_o(s0_dat_i),
.dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb),
.dwb_sel_i(s0_sel));
assign s0_err = 1'b0;
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