[Commit-gnuradio] r8259 - usrp2/trunk/fpga/top/u2_rev2

[matt]

Author: matt
Date: 2008-04-23 16:35:19 -0600 (Wed, 23 Apr 2008)
New Revision: 8259

Modified:
   usrp2/trunk/fpga/top/u2_rev2/u2_rev2.ise
   usrp2/trunk/fpga/top/u2_rev2/u2_rev2.prj
   usrp2/trunk/fpga/top/u2_rev2/u2_rev2.v
Log:
now does 24K RAM, but synthesizes as a full 32K


Modified: usrp2/trunk/fpga/top/u2_rev2/u2_rev2.ise
===================================================================
(Binary files differ)

Modified: usrp2/trunk/fpga/top/u2_rev2/u2_rev2.prj
===================================================================
--- usrp2/trunk/fpga/top/u2_rev2/u2_rev2.prj    2008-04-23 22:07:34 UTC (rev 
8258)
+++ usrp2/trunk/fpga/top/u2_rev2/u2_rev2.prj    2008-04-23 22:35:19 UTC (rev 
8259)
@@ -5,7 +5,6 @@
 verilog work "../../control_lib/gray_send.v"
 verilog work "../../opencores/uart16550/rtl/verilog/uart_tfifo.v"
 verilog work "../../opencores/uart16550/rtl/verilog/uart_rfifo.v"
-verilog work "../../coregen/fifo_generator_v4_1.v"
 verilog work "../../control_lib/shortfifo.v"
 verilog work "../../control_lib/longfifo.v"
 verilog work "../../control_lib/fifo_2clock.v"

Modified: usrp2/trunk/fpga/top/u2_rev2/u2_rev2.v
===================================================================
--- usrp2/trunk/fpga/top/u2_rev2/u2_rev2.v      2008-04-23 22:07:34 UTC (rev 
8258)
+++ usrp2/trunk/fpga/top/u2_rev2/u2_rev2.v      2008-04-23 22:35:19 UTC (rev 
8259)
@@ -298,7 +298,8 @@
       .S(0)       // Synchronous preset input
       );
    */
-   u2_core u2_core(.dsp_clk           (dsp_clk),
+   u2_core #(.RAM_SIZE(24576))
+       u2_core(.dsp_clk           (dsp_clk),
                     .wb_clk            (wb_clk),
                     .clock_ready       (clock_ready),
                     .clk_to_mac        (clk_to_mac),