[Commit-gnuradio] r8268 - usrp2/trunk/fpga/top/u2_rev2

[matt]

Author: matt
Date: 2008-04-24 11:44:37 -0600 (Thu, 24 Apr 2008)
New Revision: 8268

Modified:
   usrp2/trunk/fpga/top/u2_rev2/u2_rev2.ise
   usrp2/trunk/fpga/top/u2_rev2/u2_rev2.prj
   usrp2/trunk/fpga/top/u2_rev2/u2_rev2.v
Log:
don't connect uart rx due to timing problems


Modified: usrp2/trunk/fpga/top/u2_rev2/u2_rev2.ise
===================================================================
(Binary files differ)

Modified: usrp2/trunk/fpga/top/u2_rev2/u2_rev2.prj
===================================================================
--- usrp2/trunk/fpga/top/u2_rev2/u2_rev2.prj    2008-04-24 06:17:04 UTC (rev 
8267)
+++ usrp2/trunk/fpga/top/u2_rev2/u2_rev2.prj    2008-04-24 17:44:37 UTC (rev 
8268)
@@ -5,6 +5,7 @@
 verilog work "../../control_lib/gray_send.v"
 verilog work "../../opencores/uart16550/rtl/verilog/uart_tfifo.v"
 verilog work "../../opencores/uart16550/rtl/verilog/uart_rfifo.v"
+verilog work "../../coregen/fifo_generator_v4_1.v"
 verilog work "../../control_lib/shortfifo.v"
 verilog work "../../control_lib/longfifo.v"
 verilog work "../../control_lib/fifo_2clock.v"

Modified: usrp2/trunk/fpga/top/u2_rev2/u2_rev2.v
===================================================================
--- usrp2/trunk/fpga/top/u2_rev2/u2_rev2.v      2008-04-24 06:17:04 UTC (rev 
8267)
+++ usrp2/trunk/fpga/top/u2_rev2/u2_rev2.v      2008-04-24 17:44:37 UTC (rev 
8268)
@@ -385,7 +385,7 @@
                     .RAM_OEn           (RAM_OEn),
                     .RAM_LDn           (RAM_LDn), 
                     .uart_tx_o         (uart_tx_o),
-                    //.uart_rx_i         (uart_rx_i),
+                    //.uart_rx_i         (uart_rx_i),  the rx side causes 
timing problems
                     .uart_rx_i         (),
                     .uart_baud_o       (),
                     .sim_mode          (1'b0),