[Commit-gnuradio] r8288 - usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx

[matt]

Author: matt
Date: 2008-04-29 11:00:51 -0600 (Tue, 29 Apr 2008)
New Revision: 8288

Modified:
   usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v
Log:
use the xilinx fifo in both synthesis and sims now that icarus understands it


Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v 2008-04-29 16:59:16 UTC 
(rev 8287)
+++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v 2008-04-29 17:00:51 UTC 
(rev 8288)
@@ -117,16 +117,16 @@
    wire [RX_FF_DEPTH-1:0] occupied;
    wire [31:0]            dataout;
 
-   /*
+/*
    fifo_2clock #(.DWIDTH(36),.AWIDTH(RX_FF_DEPTH)) mac_rx_fifo
      (.wclk(Clk_MAC),.datain((PKT_state==PKT_err) ? 36'hF_FFFF_FFFF : 
staging2),.write(~Fifo_full & (line_ready_d1|(PKT_state==PKT_err))),
       .full(Fifo_full),.level_wclk(occupied),
       
.rclk(Clk_SYS),.dataout({sop_o,eop_o,be_o[1:0],dataout}),.read(Rx_mac_rd),
       .empty(empty),.level_rclk(),
       .arst(Reset) );
-   */
-   
-   fifo_generator_v4_1 fifo_generator_v4_1 
+  */
+ 
+    fifo_generator_v4_1 fifo_generator_v4_1 
      (
       .din((PKT_state==PKT_err) ? 36'hF_FFFF_FFFF : staging2), // Bus [35 : 0] 
       .rd_clk(Clk_SYS),
@@ -139,7 +139,6 @@
       .full(Fifo_full),
       .rd_data_count(), // Bus [11 : 0] 
       .wr_data_count(occupied)); // Bus [11 : 0] 
-
    
    assign         Fifo_space[15:RX_FF_DEPTH] = 0;
    assign         Fifo_space[RX_FF_DEPTH-1:0] = ~occupied;