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[Commit-gnuradio] r8438 - gnuradio/branches/developers/gnychis/fpga/usrp
From: |
gnychis |
Subject: |
[Commit-gnuradio] r8438 - gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches |
Date: |
Sat, 17 May 2008 12:14:08 -0600 (MDT) |
Author: gnychis
Date: 2008-05-17 12:14:07 -0600 (Sat, 17 May 2008)
New Revision: 8438
Added:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/ad9862.v
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/fx2.v
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/usrp_inband_usb_tb.v
Log:
starting to add simulation files for all components
Added:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/ad9862.v
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/ad9862.v
(rev 0)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/ad9862.v
2008-05-17 18:14:07 UTC (rev 8438)
@@ -0,0 +1,13 @@
+module ad9862 (
+ input SCLK,
+ input SDI,
+ output SDO,
+
+ input TXSYNC,
+ input TX,
+
+ output DA,
+ output DB
+) ;
+
+endmodule
Added:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/fx2.v
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/fx2.v
(rev 0)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/fx2.v
2008-05-17 18:14:07 UTC (rev 8438)
@@ -0,0 +1,22 @@
+module fx2 (
+ output fx2_1,
+ input fx2_2,
+ input fx2_3,
+
+ output usbclk,
+ output [2:0] usbctl,
+ output [1:0] usbrdy,
+ inout [15:0] usbdata
+) ;
+
+ initial begin
+ usbclk = 0 ;
+ fx2_1 = 0 ;
+ usbctl = 3'd0 ;
+ usbrdy = 2'd0 ;
+ usbdata = 16'd0 ;
+ end
+
+ always #(1.0/24.0) usbclk = ~usbclk ;
+
+endmodule
Added:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/usrp_inband_usb_tb.v
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/usrp_inband_usb_tb.v
(rev 0)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/usrp_inband_usb_tb.v
2008-05-17 18:14:07 UTC (rev 8438)
@@ -0,0 +1,129 @@
+`timescale 1ns/10ps
+
+module usrp_inband_usb_tb( ) ;
+
+ // FX2 Random Signals
+ wire fx2_1 ;
+ wire fx2_2 ;
+ wire fx2_3 ;
+
+ // FX2 USB Signals
+ wire usbclk ;
+ wire [2:0] usbctl ;
+ wire [1:0] usbrdy ;
+ wire [15:0] usbdata ;
+
+ // FPGA Top Level Signals
+ wire MYSTERY_SIGNAL ;
+ wire master_clk ;
+
+ wire SCLK ;
+ wire SDI ;
+ wire SDO ;
+
+ wire SEN_FPGA ;
+
+ wire [11:0] rx_a_a ;
+ wire [11:0] rx_b_a ;
+ wire [11:0] rx_a_b ;
+ wire [11:0] rx_b_b ;
+
+ wire [13:0] tx_a ;
+ wire [13:0] tx_b ;
+
+ wire TXSYNC_A ;
+ wire TXSYNC_B ;
+
+ // FX2 Model for controlling USB packet information
+ fx2 fx2_model (
+ .fx2_1 ( fx2_1 ),
+ .fx2_2 ( fx2_2 ),
+ .fx2_3 ( fx2_3 ),
+ .usbclk ( usbclk ),
+ .usbctl ( usbctl ),
+ .usbrdy ( usbrdy ),
+ .usbdata ( usbdata )
+ ) ;
+
+
+ // The Design Under Test to make sure it works
+ usrp_inband_usb usrp_inband_usb_model (
+ // Mystery and Master Clock
+ .MYSTERY_SIGNAL ( MYSTERY_SIGNAL ),
+ .master_clk ( master_clk ),
+
+ // SPI Interface
+ .SCLK ( SCLK ),
+ .SDI ( SDI ),
+ .SDO ( SDO ),
+
+ // No Idea
+ .SEN_FPGA ( SEN_FPGA ),
+
+ // Random FX2 Pins
+ .FX2_1 ( fx2_1 ),
+ .FX2_2 ( fx2_2 ),
+ .FX2_3 ( fx2_3 ),
+
+ // 12-bit RX Samples
+ .rx_a_a ( rx_a_a ),
+ .rx_b_a ( rx_b_a ),
+ .rx_a_b ( rx_a_b ),
+ .rx_b_b ( rx_b_b ),
+
+ // 14-bit TX samples
+ .tx_a ( tx_a ),
+ .tx_b ( tx_b ),
+
+ // Transmit Synchronization pins
+ .TXSYNC_A ( TXSYNC_A ),
+ .TXSYNC_B ( TXSYNC_B ),
+
+ // USB Interface
+ .usbclk ( usbclk ),
+ .usbctl ( usbctl ),
+ .usbrdy ( usbrdy ),
+ .usbdata ( usbdata ),
+
+ // General purpose IO to dboard slots
+ .io_tx_a ( io_tx_a ),
+ .io_tx_b ( io_tx_b ),
+ .io_rx_a ( io_rx_a ),
+ .io_rx_b ( io_rx_b )
+ ) ;
+
+ // The A-side AD9862 MxFE
+ ad9862 ad9862_a_side_model (
+ .SCLK ( SCLK ),
+ .SDO ( SDO ),
+ .SDI ( SDI ),
+ .SEN_CODEC ( ),
+ .RESET_CODEC ( ),
+ .TXSYNC ( TX_SYNC_A ),
+ .TX ( tx_a ),
+ .DA ( rx_a_a ),
+ .DB ( rx_a_b )
+ ) ;
+
+ // The B-Side AD9862 MxFE
+ ad9862 ad9862_b_side_model (
+ .SCLK ( SCLK ),
+ .SDO ( SDO ),
+ .SDI ( SDI ),
+ .SEN_CODEC ( ),
+ .RESET_CODEC ( ),
+ .TXSYNC ( TX_SYNC_B ),
+ .TX ( tx_b ),
+ .DA ( rx_b_a ),
+ .DB ( rx_b_b )
+ ) ;
+
+ // Initialize clocks
+ initial begin
+ master_clk = 0 ;
+ end
+
+ // Toggle the clocks here
+ always #(1.0/64.0) master_clk = ~master_clk ;
+
+endmodule
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