[Commit-gnuradio] r8632 - usrp2/trunk/fpga/sdr_lib

[matt]

Author: matt
Date: 2008-06-19 15:33:12 -0600 (Thu, 19 Jun 2008)
New Revision: 8632

Modified:
   usrp2/trunk/fpga/sdr_lib/dsp_core_tx.v
   usrp2/trunk/fpga/sdr_lib/tx_control.v
Log:
moved strobes out of tx_control, into dsp_core_tx, added halfbands to tx (just 
passthru for now), changed scaling so everything is 18 bits wide.


Modified: usrp2/trunk/fpga/sdr_lib/dsp_core_tx.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/dsp_core_tx.v      2008-06-19 21:14:37 UTC (rev 
8631)
+++ usrp2/trunk/fpga/sdr_lib/dsp_core_tx.v      2008-06-19 21:33:12 UTC (rev 
8632)
@@ -11,7 +11,7 @@
    // To tx_control
    input [31:0] sample,
    input run,
-   input strobe
+   output strobe
    );
    
    wire [15:0] i, q, scale_i, scale_q;
@@ -19,51 +19,72 @@
    reg [31:0]  phase;
    wire [7:0]  interp_rate;
 
-   setting_reg #(.my_addr(`DSP_CORE_TX_BASE+2)) sr_2
-     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(interp_rate),.changed());
-
+   wire        strobe_cic, strobe_hb1, strobe_hb2;
+   assign      strobe = strobe_hb2;
+   wire        enable_hb1, enable_hb2;
+   
    setting_reg #(.my_addr(`DSP_CORE_TX_BASE+0)) sr_0
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(phase_inc),.changed());
-   
+
    setting_reg #(.my_addr(`DSP_CORE_TX_BASE+1)) sr_1
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out({scale_i,scale_q}),.changed());
    
+   setting_reg #(.my_addr(`DSP_CORE_TX_BASE+2)) sr_2
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({/*enable_hb1,enable_hb2, */ 
interp_rate}),.changed());
+
+   assign      enable_hb1 = 0;
+   assign      enable_hb2 = 0;
+   
    always @(posedge clk)
      if(rst)
        phase <= 0;
      else if(run)
        phase <= phase + phase_inc;
    
-   wire        signed [15:0] da, db;
-   reg                signed [15:0] dar, dbr;
-   
+   wire        signed [17:0] da, db;
    wire        signed [35:0] prod_i, prod_q;
 
-   wire [15:0] bb_i = sample[31:16];
-   wire [15:0] bb_q = sample[15:0];
-   wire [15:0] i_interp, q_interp;
+   wire [17:0] bb_i = {sample[31:16],2'b0};
+   wire [17:0] bb_q = {sample[15:0],2'b0};
+   wire [17:0] i_interp, q_interp;
+
+   wire [17:0] hb1_i, hb1_q, hb2_i, hb2_q;
    
-   cic_interp  #(.bw(16),.N(4),.log2_of_max_rate(7))
+   hb_interp #(.WIDTH(18)) hb_interp_i
+     
(.clk(clk),.rst(rst),.bypass(~enable_hb1),.stb_in(strobe_hb2),.data_in(bb_i),.stb_out(strobe_hb1),.data_out(hb1_i));
+   hb_interp #(.WIDTH(18)) hb_interp_q
+     
(.clk(clk),.rst(rst),.bypass(~enable_hb1),.stb_in(strobe_hb2),.data_in(bb_q),.stb_out(),.data_out(hb1_q));
+   
+   small_hb_int #(.WIDTH(18)) small_hb_interp_i
+     
(.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_cic),.data_in(hb1_i),.stb_out(strobe_hb2),.data_out(hb2_i));
+   small_hb_int #(.WIDTH(18)) small_hb_interp_q
+     
(.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_cic),.data_in(hb1_q),.stb_out(),.data_out(hb2_q));
+   
+   cic_strober 
cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate),
+                          .strobe_fast(1),.strobe_slow(strobe_cic) );
+   
+   cic_interp  #(.bw(18),.N(4),.log2_of_max_rate(7))
      cic_interp_i(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate),
-                 .strobe_in(strobe),.strobe_out(1),
-                 .signal_in(bb_i),.signal_out(i_interp));
+                 .strobe_in(strobe_cic),.strobe_out(1),
+                 .signal_in(hb2_i),.signal_out(i_interp));
    
-   cic_interp  #(.bw(16),.N(4),.log2_of_max_rate(7))
+   cic_interp  #(.bw(18),.N(4),.log2_of_max_rate(7))
      cic_interp_q(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate),
-                 .strobe_in(strobe),.strobe_out(1),
-                 .signal_in(bb_q),.signal_out(q_interp));
-   
-   cordic #(.bitwidth(16),.zwidth(16))
+                 .strobe_in(strobe_cic),.strobe_out(1),
+                 .signal_in(hb2_q),.signal_out(q_interp));
+
+      
+   cordic #(.bitwidth(18),.zwidth(16))
      cordic(.clock(clk), .reset(rst), .enable(run),
            .xi(i_interp),.yi(q_interp),.zi(phase[31:16]),
            .xo(da),.yo(db),.zo() );
    
    MULT18X18S MULT18X18S_inst 
      (.P(prod_i),    // 36-bit multiplier output
-      .A({{2{da[15]}},da} ),    // 18-bit multiplier input
+      .A(da),    // 18-bit multiplier input
       .B({{2{scale_i[15]}},scale_i}),    // 18-bit multiplier input
       .C(clk),    // Clock input
       .CE(1),  // Clock enable input
@@ -72,7 +93,7 @@
    
    MULT18X18S MULT18X18S_inst_2 
      (.P(prod_q),    // 36-bit multiplier output
-      .A({{2{db[15]}},db} ),    // 18-bit multiplier input
+      .A(db),    // 18-bit multiplier input
       .B({{2{scale_q[15]}},scale_q}),    // 18-bit multiplier input
       .C(clk),    // Clock input
       .CE(1),  // Clock enable input
@@ -80,9 +101,9 @@
       );
    
    always @(posedge clk)
-     dac_a <= prod_i[23:8];
+     dac_a <= prod_i[28:13];
    
    always @(posedge clk)
-     dac_b <= prod_q[23:8];
-   
+     dac_b <= prod_q[28:13];
+
 endmodule // dsp_core

Modified: usrp2/trunk/fpga/sdr_lib/tx_control.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/tx_control.v       2008-06-19 21:14:37 UTC (rev 
8631)
+++ usrp2/trunk/fpga/sdr_lib/tx_control.v       2008-06-19 21:33:12 UTC (rev 
8632)
@@ -20,7 +20,7 @@
      // To DSP Core
      output [31:0] sample,
      output run,
-     output strobe,
+     input strobe,
 
      output [31:0] debug
      );
@@ -137,13 +137,6 @@
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(),.changed(clear_state));
 
-   setting_reg #(.my_addr(`DSP_CORE_TX_BASE+2)) sr_2
-     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(interp_rate),.changed());
-
-   strobe_gen 
strobe_gen(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate),
-                        .strobe_in(run),.strobe(strobe) );
-
    assign      sample = data_o;
 
    assign      debug = { 16'd0,