[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Commit-gnuradio] r8686 - in usrp2/trunk/fpga/top: . tcl u2_rev2
|
From: |
matt |
|
Subject: |
[Commit-gnuradio] r8686 - in usrp2/trunk/fpga/top: . tcl u2_rev2 |
|
Date: |
Tue, 24 Jun 2008 12:00:39 -0600 (MDT) |
Author: matt
Date: 2008-06-24 12:00:26 -0600 (Tue, 24 Jun 2008)
New Revision: 8686
Added:
usrp2/trunk/fpga/top/tcl/
usrp2/trunk/fpga/top/tcl/ise_helper.tcl
Modified:
usrp2/trunk/fpga/top/u2_rev2/Makefile
usrp2/trunk/fpga/top/u2_rev2/u2_rev2.ucf
Log:
makefile for u2_rev2
Added: usrp2/trunk/fpga/top/tcl/ise_helper.tcl
===================================================================
--- usrp2/trunk/fpga/top/tcl/ise_helper.tcl (rev 0)
+++ usrp2/trunk/fpga/top/tcl/ise_helper.tcl 2008-06-24 18:00:26 UTC (rev
8686)
@@ -0,0 +1,87 @@
+#
+# Copyright 2008 Free Software Foundation, Inc.
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+
+proc set_props {process options} {
+ if ![string compare $options ""] {
+ return
+ }
+ set state 1
+ foreach opt $options {
+ if $state {
+ set key $opt
+ set state 0
+ } else {
+ puts ">>> Setting: $process\[$key\] = $opt"
+ if ![string compare $process "Project"] {
+ project set $key $opt
+ } else {
+ project set $key $opt -process $process
+ }
+ set state 1
+ }
+ }
+}
+
+if [file isfile $env(PROJ_FILE)] {
+ puts ">>> Opening project: $env(PROJ_FILE)"
+ project open $env(PROJ_FILE)
+} else {
+ puts ">>> Creating project: $env(PROJ_FILE)"
+ project new $env(PROJ_FILE)
+
+ ##################################################
+ # Set the project properties
+ ##################################################
+ set_props "Project" $env(PROJECT_PROPERTIES)
+
+ ##################################################
+ # Add the sources
+ ##################################################
+ foreach source $env(SOURCES) {
+ set source $env(SOURCE_ROOT)$source
+ puts ">>> Adding source to project: $source"
+ xfile add $source
+ }
+
+ ##################################################
+ # Set the top level module
+ ##################################################
+ project set top $env(TOP_MODULE)
+
+ ##################################################
+ # Set the process properties
+ ##################################################
+ set_props "Synthesize - XST" $env(SYNTHESIZE_PROPERTIES)
+ set_props "Translate" $env(TRANSLATE_PROPERTIES)
+ set_props "Map" $env(MAP_PROPERTIES)
+ set_props "Place & Route" $env(PLACE_ROUTE_PROPERTIES)
+ set_props "Generate Post-Place & Route Static Timing"
$env(STATIC_TIMING_PROPERTIES)
+ set_props "Generate Programming File" $env(GEN_PROG_FILE_PROPERTIES)
+ set_props "Generate Post-Place & Route Simulation Model"
$env(SIM_MODEL_PROPERTIES)
+}
+
+if [string compare $env(PROCESS_RUN) ""] {
+ puts ">>> Running Process: $env(PROCESS_RUN)"
+ process run $env(PROCESS_RUN)
+}
+
+project close
+exit
Modified: usrp2/trunk/fpga/top/u2_rev2/Makefile
===================================================================
--- usrp2/trunk/fpga/top/u2_rev2/Makefile 2008-06-23 23:03:43 UTC (rev
8685)
+++ usrp2/trunk/fpga/top/u2_rev2/Makefile 2008-06-24 18:00:26 UTC (rev
8686)
@@ -1,129 +1,214 @@
-FILENAME=u2_rev2
-PARTNUM=xc3s2000-5fg456
+#
+# Copyright 2008 Free Software Foundation, Inc.
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
-all: project command xst ngd ncd ncd2 bit
+##################################################
+# xtclsh Shell and tcl Script Path
+##################################################
+XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
+ISE_HELPER := $(shell pwd)/../tcl/ise_helper.tcl
-xst:
- xst -ifn ${FILENAME}.cmd -ofn xst.log
+##################################################
+# Project Setup
+##################################################
+BUILD_DIR := $(shell pwd)/build/
+export TOP_MODULE := u2_rev2
+export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
-ngd:
- ngdbuild -nt timestamp -p ${PARTNUM} ${FILENAME}
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family spartan3 \
+device xc3s2000 \
+package fg456 \
+speed -5
-ncd:
- rm -rf ${FILENAME}.ncd
- map -detail -cm speed -k 8 -retiming on -equivalent_register_removal on
-timing -ol high -pr b -p ${PARTNUM} ${FILENAME}.ngd -o ${FILENAME}.ncd
${FILENAME}.pcf
+##################################################
+# Sources
+##################################################
+export SOURCE_ROOT := $(shell pwd)/../../
+export SOURCES := \
+control_lib/CRC16_D16.v \
+control_lib/atr_controller.v \
+control_lib/bin2gray.v \
+control_lib/buffer_int.v \
+control_lib/buffer_pool.v \
+control_lib/cascadefifo2.v \
+control_lib/dcache.v \
+control_lib/decoder_3_8.v \
+control_lib/dpram32.v \
+control_lib/extram_interface.v \
+control_lib/fifo_2clock.v \
+control_lib/fifo_2clock_casc.v \
+control_lib/gray2bin.v \
+control_lib/gray_send.v \
+control_lib/icache.v \
+control_lib/longfifo.v \
+control_lib/mux4.v \
+control_lib/mux8.v \
+control_lib/nsgpio.v \
+control_lib/ram_2port.v \
+control_lib/ram_harv_cache.v \
+control_lib/ram_loader.v \
+control_lib/setting_reg.v \
+control_lib/settings_bus.v \
+control_lib/shortfifo.v \
+control_lib/srl.v \
+control_lib/system_control.v \
+control_lib/wb_1master.v \
+control_lib/wb_readback_mux.v \
+coregen/fifo_generator_v4_1.v \
+eth/mac_rxfifo_int.v \
+eth/mac_txfifo_int.v \
+eth/rtl/verilog/Clk_ctrl.v \
+eth/rtl/verilog/MAC_rx.v \
+eth/rtl/verilog/MAC_rx/Broadcast_filter.v \
+eth/rtl/verilog/MAC_rx/CRC_chk.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \
+eth/rtl/verilog/MAC_top.v \
+eth/rtl/verilog/MAC_tx.v \
+eth/rtl/verilog/MAC_tx/CRC_gen.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \
+eth/rtl/verilog/MAC_tx/Random_gen.v \
+eth/rtl/verilog/Phy_int.v \
+eth/rtl/verilog/RMON.v \
+eth/rtl/verilog/RMON/RMON_addr_gen.v \
+eth/rtl/verilog/RMON/RMON_ctrl.v \
+eth/rtl/verilog/Reg_int.v \
+eth/rtl/verilog/eth_miim.v \
+eth/rtl/verilog/flow_ctrl_rx.v \
+eth/rtl/verilog/flow_ctrl_tx.v \
+eth/rtl/verilog/miim/eth_clockgen.v \
+eth/rtl/verilog/miim/eth_outputcontrol.v \
+eth/rtl/verilog/miim/eth_shiftreg.v \
+opencores/8b10b/decode_8b10b.v \
+opencores/8b10b/encode_8b10b.v \
+opencores/aemb/rtl/verilog/aeMB_bpcu.v \
+opencores/aemb/rtl/verilog/aeMB_core_BE.v \
+opencores/aemb/rtl/verilog/aeMB_ctrl.v \
+opencores/aemb/rtl/verilog/aeMB_edk32.v \
+opencores/aemb/rtl/verilog/aeMB_ibuf.v \
+opencores/aemb/rtl/verilog/aeMB_regf.v \
+opencores/aemb/rtl/verilog/aeMB_xecu.v \
+opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_defines.v \
+opencores/i2c/rtl/verilog/i2c_master_top.v \
+opencores/i2c/rtl/verilog/timescale.v \
+opencores/simple_pic/rtl/simple_pic.v \
+opencores/spi/rtl/verilog/spi_clgen.v \
+opencores/spi/rtl/verilog/spi_defines.v \
+opencores/spi/rtl/verilog/spi_shift.v \
+opencores/spi/rtl/verilog/spi_top.v \
+opencores/spi/rtl/verilog/timescale.v \
+opencores/uart16550/rtl/verilog/raminfr.v \
+opencores/uart16550/rtl/verilog/timescale.v \
+opencores/uart16550/rtl/verilog/uart_debug_if.v \
+opencores/uart16550/rtl/verilog/uart_defines.v \
+opencores/uart16550/rtl/verilog/uart_receiver.v \
+opencores/uart16550/rtl/verilog/uart_regs.v \
+opencores/uart16550/rtl/verilog/uart_rfifo.v \
+opencores/uart16550/rtl/verilog/uart_sync_flops.v \
+opencores/uart16550/rtl/verilog/uart_tfifo.v \
+opencores/uart16550/rtl/verilog/uart_top.v \
+opencores/uart16550/rtl/verilog/uart_transmitter.v \
+opencores/uart16550/rtl/verilog/uart_wb.v \
+sdr_lib/acc.v \
+sdr_lib/add2.v \
+sdr_lib/add2_and_round.v \
+sdr_lib/add2_and_round_reg.v \
+sdr_lib/add2_reg.v \
+sdr_lib/cic_dec_shifter.v \
+sdr_lib/cic_decim.v \
+sdr_lib/cic_int_shifter.v \
+sdr_lib/cic_interp.v \
+sdr_lib/cic_strober.v \
+sdr_lib/clip.v \
+sdr_lib/clip_reg.v \
+sdr_lib/cordic.v \
+sdr_lib/cordic_stage.v \
+sdr_lib/dsp_core_rx.v \
+sdr_lib/dsp_core_tx.v \
+sdr_lib/hb_dec.v \
+sdr_lib/hb_interp.v \
+sdr_lib/round.v \
+sdr_lib/round_reg.v \
+sdr_lib/rx_control.v \
+sdr_lib/rx_dcoffset.v \
+sdr_lib/sign_extend.v \
+sdr_lib/small_hb_dec.v \
+sdr_lib/small_hb_int.v \
+sdr_lib/tx_control.v \
+serdes/serdes.v \
+serdes/serdes_fc_rx.v \
+serdes/serdes_fc_tx.v \
+serdes/serdes_rx.v \
+serdes/serdes_tx.v \
+timing/time_receiver.v \
+timing/time_sender.v \
+timing/time_sync.v \
+timing/timer.v \
+top/u2_core/u2_core.v \
+top/u2_rev2/u2_rev2.ucf \
+top/u2_rev2/u2_rev2.v
-# Place and route ncd file into new ncd file
-ncd2:
- par -ol high -xe n -w ${FILENAME}.ncd ${FILENAME} ${FILENAME}.pcf
+##################################################
+# Process Properties
+##################################################
+export SYNTHESIZE_PROPERTIES := ""
-bit:
- bitgen -w ${FILENAME}.ncd -b ${FILENAME}.bit
+export TRANSLATE_PROPERTIES := \
+"macro search path" "$(SOURCE_ROOT)/coregen/"
-clean:
- @rm -rf ${FILENAME}.ngc *.lst *.bit *.lso *.xst *.stx *.syr \
- *.ngr *.cmd_log _ngc _xmsgs xst *.html *.srp \
- *.blc *.bld *.ise_ISE_Backup *~ \
- *.pad *.ngm *.ngd *.par *.pcf *.unroutes \
- *.xpi *.bgn *.drc *.bin *.mrp *.csv *.txt \
- *.rbt *.ncd ${FILENAME} *_cg templates/ tmp/ \
- output.dat coregen.log *.ngo *.log ${FILENAME}.map \
- ${FILENAME}_summary.xml ${FILENAME}_usage.xml ${FILENAME}.twr
+export MAP_PROPERTIES := ""
-command:
- rm -rf ${FILENAME}.cmd
- @echo "identification" >> ${FILENAME}.cmd
- @echo "status" >> ${FILENAME}.cmd
- @echo "time short" >> ${FILENAME}.cmd
- @echo "memory on" >> ${FILENAME}.cmd
- @echo "run " >> ${FILENAME}.cmd
- @echo "-top ${FILENAME}" >> ${FILENAME}.cmd
- @echo "-ifn ${FILENAME}.prj" >> ${FILENAME}.cmd
- @echo "-ifmt Verilog " >> ${FILENAME}.cmd
- @echo "-ofn ${FILENAME} " >> ${FILENAME}.cmd
- @echo "-p ${PARTNUM}" >> ${FILENAME}.cmd
- @echo "-bufg 6" >> ${FILENAME}.cmd
- @echo "-vlgincdir { ../../opencores/i2c/rtl/verilog
../../eth/rtl/verilog/ ../../opencores/spi/rtl/verilog}" >> ${FILENAME}.cmd
+export PLACE_ROUTE_PROPERTIES := ""
-project:
- rm -f ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/TECH/duram.v" '
>> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/sign_extend.v" '
>> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/cordic_stage.v" '
>> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/cic_int_shifter.v" '
>> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/cic_dec_shifter.v" '
>> ${FILENAME}.prj
- @echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v"
' >> ${FILENAME}.prj
- @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_regfile.v" '
>> ${FILENAME}.prj
- @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_fetch.v" '
>> ${FILENAME}.prj
- @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_decode.v" '
>> ${FILENAME}.prj
- @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_control.v" '
>> ${FILENAME}.prj
- @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_aslu.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/miim/eth_shiftreg.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/miim/eth_outputcontrol.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/miim/eth_clockgen.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/TECH/eth_clk_switch.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/TECH/eth_clk_div2.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/Reg_int.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/RMON/RMON_dpram.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/RMON/RMON_ctrl.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/RMON/RMON_addr_gen.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_tx/flow_ctrl.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_tx/Ramdon_gen.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_FF.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_tx/CRC_gen.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_rx/CRC_chk.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v" '
>> ${FILENAME}.prj
- @echo '`include "../../control_lib/ram_2port.v" '
>> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/cordic.v" '
>> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/cic_interp.v" '
>> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/cic_decim.v" '
>> ${FILENAME}.prj
- @echo '`include "../../opencores/spi/rtl/verilog/spi_shift.v" '
>> ${FILENAME}.prj
- @echo '`include "../../opencores/spi/rtl/verilog/spi_clgen.v" '
>> ${FILENAME}.prj
- @echo '`include
"../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v" ' >>
${FILENAME}.prj
- @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_core.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/eth_miim.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/RMON.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/Phy_int.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_tx.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_rx.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/Clk_ctrl.v" '
>> ${FILENAME}.prj
- @echo '`include "../../control_lib/strobe_gen.v" '
>> ${FILENAME}.prj
- @echo '`include "../../control_lib/ss_rcvr.v" '
>> ${FILENAME}.prj
- @echo '`include "../../control_lib/shortfifo.v" '
>> ${FILENAME}.prj
- @echo '`include "../../control_lib/setting_reg.v" '
>> ${FILENAME}.prj
- @echo '`include "../../control_lib/mux8.v" '
>> ${FILENAME}.prj
- @echo '`include "../../control_lib/mux4.v" '
>> ${FILENAME}.prj
- @echo '`include "../../control_lib/longfifo.v" '
>> ${FILENAME}.prj
- @echo '`include "../../control_lib/decoder_3_8.v" '
>> ${FILENAME}.prj
- @echo '`include "../../control_lib/buffer_int.v" '
>> ${FILENAME}.prj
- @echo '`include "../../control_lib/CRC16_D16.v" '
>> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/tx_control.v" '
>> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/rx_control.v" '
>> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/dsp_core_tx.v" '
>> ${FILENAME}.prj
- @echo '`include "../../sdr_lib/dsp_core_rx.v" '
>> ${FILENAME}.prj
- @echo '`include "../../opencores/spi/rtl/verilog/spi_top.v" '
>> ${FILENAME}.prj
- @echo '`include "../../opencores/simple_pic/rtl/simple_pic.v" '
>> ${FILENAME}.prj
- @echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_top.v" '
>> ${FILENAME}.prj
- @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_core_BE.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/MAC_top.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/mac_txfifo_int.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/mac_rxfifo_int.v" '
>> ${FILENAME}.prj
- @echo '`include "../../control_lib/wb_readback_mux.v" '
>> ${FILENAME}.prj
- @echo '`include "../../control_lib/wb_1master.v" '
>> ${FILENAME}.prj
- @echo '`include "../../control_lib/timer.v" '
>> ${FILENAME}.prj
- @echo '`include "../../control_lib/system_control.v" '
>> ${FILENAME}.prj
- @echo '`include "../../control_lib/settings_bus.v" '
>> ${FILENAME}.prj
- @echo '`include "../../control_lib/serdes_tx.v" '
>> ${FILENAME}.prj
- @echo '`include "../../control_lib/serdes_rx.v" '
>> ${FILENAME}.prj
- @echo '`include "../../control_lib/ram_wb_harvard.v" '
>> ${FILENAME}.prj
- @echo '`include "../../control_lib/ram_loader.v" '
>> ${FILENAME}.prj
- @echo '`include "../../control_lib/nsgpio.v" '
>> ${FILENAME}.prj
- @echo '`include "../../control_lib/buffer_pool.v" '
>> ${FILENAME}.prj
- @echo '`include "../u2_basic/u2_basic.v" '
>> ${FILENAME}.prj
- @echo '`include "u2_rev2.v" '
>> ${FILENAME}.prj
- @echo '`include "../../eth/rtl/verilog/elastic_buffer.v" '
>> ${FILENAME}.prj
+export STATIC_TIMING_PROPERTIES := ""
+
+export GEN_PROG_FILE_PROPERTIES := ""
+
+export SIM_MODEL_PROPERTIES := ""
+
+##################################################
+# Make Options
+##################################################
+all:
+ @echo make proj, check, synth, or bin
+
+proj:
+ PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)
+
+check:
+ PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)
+
+synth:
+ PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)
+
+bin:
+ PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)
+
+clean:
+ rm -rf $(BUILD_DIR)
Property changes on: usrp2/trunk/fpga/top/u2_rev2/u2_rev2.ucf
___________________________________________________________________
Name: svn:executable
- *
| [Prev in Thread] |
Current Thread |
[Next in Thread] |
- [Commit-gnuradio] r8686 - in usrp2/trunk/fpga/top: . tcl u2_rev2,
matt <=