[Commit-gnuradio] r8690 - in usrp2/trunk/fpga/top: tcl u2_rev2

[matt]

Author: matt
Date: 2008-06-24 14:56:16 -0600 (Tue, 24 Jun 2008)
New Revision: 8690

Modified:
   usrp2/trunk/fpga/top/tcl/ise_helper.tcl
   usrp2/trunk/fpga/top/u2_rev2/Makefile
Log:
updated props - resolved timing issue



Modified: usrp2/trunk/fpga/top/tcl/ise_helper.tcl
===================================================================
--- usrp2/trunk/fpga/top/tcl/ise_helper.tcl     2008-06-24 20:48:39 UTC (rev 
8689)
+++ usrp2/trunk/fpga/top/tcl/ise_helper.tcl     2008-06-24 20:56:16 UTC (rev 
8690)
@@ -1,5 +1,5 @@
 #
-# Copyright 2008 Free Software Foundation, Inc.
+# Copyright 2008 Ettus Research LLC
 # 
 # This file is part of GNU Radio
 # 
@@ -85,3 +85,5 @@
 
 project close
 exit
+
+

Modified: usrp2/trunk/fpga/top/u2_rev2/Makefile
===================================================================
--- usrp2/trunk/fpga/top/u2_rev2/Makefile       2008-06-24 20:48:39 UTC (rev 
8689)
+++ usrp2/trunk/fpga/top/u2_rev2/Makefile       2008-06-24 20:56:16 UTC (rev 
8690)
@@ -1,5 +1,5 @@
 #
-# Copyright 2008 Free Software Foundation, Inc.
+# Copyright 2008 Ettus Research LLC
 # 
 # This file is part of GNU Radio
 # 
@@ -36,10 +36,16 @@
 # Project Properties
 ##################################################
 export PROJECT_PROPERTIES := \
-family spartan3 \
+family Spartan3 \
 device xc3s2000 \
 package fg456 \
-speed -5
+speed -5 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
 
 ##################################################
 # Sources
@@ -177,18 +183,33 @@
 ##################################################
 # Process Properties
 ##################################################
-export SYNTHESIZE_PROPERTIES := ""
+export SYNTHESIZE_PROPERTIES := \
+"Number of Clock Buffers" 6 \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
 
 export TRANSLATE_PROPERTIES := \
-"macro search path" "$(SOURCE_ROOT)/coregen/"
+"Macro Search Path" "$(SOURCE_ROOT)/coregen/"
 
-export MAP_PROPERTIES := ""
+export MAP_PROPERTIES := \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" 
 
-export PLACE_ROUTE_PROPERTIES := ""
+export PLACE_ROUTE_PROPERTIES := \
+"Place & Route Effort Level (Overall)" High 
 
 export STATIC_TIMING_PROPERTIES := ""
 
-export GEN_PROG_FILE_PROPERTIES := ""
+export GEN_PROG_FILE_PROPERTIES := \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 
 
 export SIM_MODEL_PROPERTIES := ""
 
@@ -196,7 +217,7 @@
 # Make Options
 ##################################################
 all:
-       @echo make proj, check, synth, or bin
+       @echo make proj, check, synth, bin, or clean
 
 proj:
        PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)  
@@ -212,3 +233,5 @@
 
 clean:
        rm -rf $(BUILD_DIR)
+
+