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[Commit-gnuradio] r8693 - usrp2/trunk/fpga/top/u2_rev2

From: matt
Subject: [Commit-gnuradio] r8693 - usrp2/trunk/fpga/top/u2_rev2
Date: Tue, 24 Jun 2008 16:47:38 -0600 (MDT) 
Author: matt
Date: 2008-06-24 16:47:36 -0600 (Tue, 24 Jun 2008)
New Revision: 8693

Modified:
   usrp2/trunk/fpga/top/u2_rev2/u2_rev2.ucf
Log:
experimental constraints on adc input nets


Modified: usrp2/trunk/fpga/top/u2_rev2/u2_rev2.ucf
===================================================================
--- usrp2/trunk/fpga/top/u2_rev2/u2_rev2.ucf    2008-06-24 22:31:55 UTC (rev 
8692)
+++ usrp2/trunk/fpga/top/u2_rev2/u2_rev2.ucf    2008-06-24 22:47:36 UTC (rev 
8693)
@@ -45,17 +45,17 @@
 NET "exp_pps_out_n"  LOC = "V2"  ; 
 NET "GMII_COL"  LOC = "U16"  ; 
 NET "GMII_CRS"  LOC = "U17"  ; 
-NET "GMII_TXD[0]"  LOC = "W14"  | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW 
= FAST ;
-NET "GMII_TXD[1]"  LOC = "AA20"  | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW 
= FAST ;
-NET "GMII_TXD[2]"  LOC = "AB20"  | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW 
= FAST ;
-NET "GMII_TXD[3]"  LOC = "Y18"  | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW 
= FAST ;
-NET "GMII_TXD[4]"  LOC = "AA18"  | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW 
= FAST ;
-NET "GMII_TXD[5]"  LOC = "AB18"  | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW 
= FAST ;
-NET "GMII_TXD[6]"  LOC = "V17"  | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW 
= FAST ;
-NET "GMII_TXD[7]"  LOC = "W17"  | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW 
= FAST ;
-NET "GMII_TX_EN"  LOC = "Y17" | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = 
FAST ; 
-NET "GMII_TX_ER"  LOC = "V16" | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = 
FAST ; 
-NET "GMII_GTX_CLK"  LOC = "AA17" | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW 
= FAST ; 
+NET "GMII_TXD[0]"  LOC = "W14"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = 
FAST ;
+NET "GMII_TXD[1]"  LOC = "AA20"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = 
FAST ;
+NET "GMII_TXD[2]"  LOC = "AB20"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = 
FAST ;
+NET "GMII_TXD[3]"  LOC = "Y18"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = 
FAST ;
+NET "GMII_TXD[4]"  LOC = "AA18"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = 
FAST ;
+NET "GMII_TXD[5]"  LOC = "AB18"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = 
FAST ;
+NET "GMII_TXD[6]"  LOC = "V17"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = 
FAST ;
+NET "GMII_TXD[7]"  LOC = "W17"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = 
FAST ;
+NET "GMII_TX_EN"  LOC = "Y17" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = 
FAST ; 
+NET "GMII_TX_ER"  LOC = "V16" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = 
FAST ; 
+NET "GMII_GTX_CLK"  LOC = "AA17" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = 
FAST ; 
 NET "GMII_TX_CLK"  LOC = "W13"  ; 
 NET "GMII_RXD[0]"  LOC = "AA15"  ;
 NET "GMII_RXD[1]"  LOC = "AB15"  ;
@@ -68,7 +68,7 @@
 NET "GMII_RX_CLK"  LOC = "W16"  ; 
 NET "GMII_RX_DV"  LOC = "AB16"  ; 
 NET "GMII_RX_ER"  LOC = "AA16"  ; 
-NET "MDIO"  LOC = "Y16" | PULLUP ; 
+NET "MDIO"  LOC = "Y16" |PULLUP ; 
 NET "MDC"  LOC = "V18"  ; 
 NET "PHY_INTn"  LOC = "AB13"  ; 
 NET "PHY_RESETn"  LOC = "AA19"  ; 
@@ -120,25 +120,25 @@
 NET "ser_prbsen"  LOC = "AA3"  ; 
 NET "ser_loopen"  LOC = "Y4"  ; 
 NET "ser_rx_en"  LOC = "AB9"  ; 
-NET "ser_tx_clk"  LOC = "U7" | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = 
FAST ; 
-NET "ser_t[0]"  LOC = "V7"  | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = 
FAST ;
-NET "ser_t[1]"  LOC = "V10"  | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = 
FAST ;
-NET "ser_t[2]"  LOC = "AB4"  | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = 
FAST ;
-NET "ser_t[3]"  LOC = "AA4"  | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = 
FAST ;
-NET "ser_t[4]"  LOC = "Y5"  | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = 
FAST ;
-NET "ser_t[5]"  LOC = "W5"  | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = 
FAST ;
-NET "ser_t[6]"  LOC = "AB5"  | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = 
FAST ;
-NET "ser_t[7]"  LOC = "AA5"  | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = 
FAST ;
-NET "ser_t[8]"  LOC = "W6"  | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = 
FAST ;
-NET "ser_t[9]"  LOC = "V6"  | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = 
FAST ;
-NET "ser_t[10]"  LOC = "AA6"  | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = 
FAST ;
-NET "ser_t[11]"  LOC = "Y6"  | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = 
FAST ;
-NET "ser_t[12]"  LOC = "W8"  | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = 
FAST ;
-NET "ser_t[13]"  LOC = "V8"  | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = 
FAST ;
-NET "ser_t[14]"  LOC = "AB8"  | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = 
FAST ;
-NET "ser_t[15]"  LOC = "AA8"  | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = 
FAST ;
-NET "ser_tklsb"  LOC = "U10" | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = 
FAST ; 
-NET "ser_tkmsb"  LOC = "U11" | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = 
FAST ; 
+NET "ser_tx_clk"  LOC = "U7" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST 
; 
+NET "ser_t[0]"  LOC = "V7"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[1]"  LOC = "V10"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST 
;
+NET "ser_t[2]"  LOC = "AB4"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST 
;
+NET "ser_t[3]"  LOC = "AA4"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST 
;
+NET "ser_t[4]"  LOC = "Y5"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[5]"  LOC = "W5"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[6]"  LOC = "AB5"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST 
;
+NET "ser_t[7]"  LOC = "AA5"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST 
;
+NET "ser_t[8]"  LOC = "W6"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[9]"  LOC = "V6"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[10]"  LOC = "AA6"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = 
FAST ;
+NET "ser_t[11]"  LOC = "Y6"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST 
;
+NET "ser_t[12]"  LOC = "W8"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST 
;
+NET "ser_t[13]"  LOC = "V8"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST 
;
+NET "ser_t[14]"  LOC = "AB8"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = 
FAST ;
+NET "ser_t[15]"  LOC = "AA8"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = 
FAST ;
+NET "ser_tklsb"  LOC = "U10" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST 
; 
+NET "ser_tkmsb"  LOC = "U11" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST 
; 
 NET "ser_rx_clk"  LOC = "AA11"  ; 
 NET "ser_r[0]"  LOC = "AB10"  ;
 NET "ser_r[1]"  LOC = "AA10"  ;
@@ -326,3 +326,39 @@
 
 NET "GMII_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE; 
 NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE;
+INST "adc_a<0>" TNM = ADC_DATA_GRP;
+INST "adc_a<1>" TNM = ADC_DATA_GRP;
+INST "adc_a<2>" TNM = ADC_DATA_GRP;
+INST "adc_a<3>" TNM = ADC_DATA_GRP;
+INST "adc_a<4>" TNM = ADC_DATA_GRP;
+INST "adc_a<5>" TNM = ADC_DATA_GRP;
+INST "adc_a<6>" TNM = ADC_DATA_GRP;
+INST "adc_a<7>" TNM = ADC_DATA_GRP;
+INST "adc_a<8>" TNM = ADC_DATA_GRP;
+INST "adc_a<9>" TNM = ADC_DATA_GRP;
+INST "adc_a<10>" TNM = ADC_DATA_GRP;
+INST "adc_a<11>" TNM = ADC_DATA_GRP;
+INST "adc_a<12>" TNM = ADC_DATA_GRP;
+INST "adc_a<13>" TNM = ADC_DATA_GRP;
+INST "adc_b<0>" TNM = ADC_DATA_GRP;
+INST "adc_b<1>" TNM = ADC_DATA_GRP;
+INST "adc_b<2>" TNM = ADC_DATA_GRP;
+INST "adc_b<3>" TNM = ADC_DATA_GRP;
+INST "adc_b<4>" TNM = ADC_DATA_GRP;
+INST "adc_b<5>" TNM = ADC_DATA_GRP;
+INST "adc_b<6>" TNM = ADC_DATA_GRP;
+INST "adc_b<7>" TNM = ADC_DATA_GRP;
+INST "adc_b<8>" TNM = ADC_DATA_GRP;
+INST "adc_b<9>" TNM = ADC_DATA_GRP;
+INST "adc_b<10>" TNM = ADC_DATA_GRP;
+INST "adc_b<11>" TNM = ADC_DATA_GRP;
+INST "adc_b<12>" TNM = ADC_DATA_GRP;
+INST "adc_b<13>" TNM = ADC_DATA_GRP;
+INST "adc_ovf_a" TNM = ADC_DATA_GRP;
+INST "adc_ovf_b" TNM = ADC_DATA_GRP;
+
+
+TIMEGRP "ADC_REG_GRP" = INST "adc_a_reg1_0" INST "adc_a_reg1_1" INST 
"adc_a_reg1_2" INST "adc_a_reg1_3" INST "adc_a_reg1_4" INST "adc_a_reg1_5" INST 
"adc_a_reg1_6" INST "adc_a_reg1_7" INST "adc_a_reg1_8" INST "adc_a_reg1_9" INST 
"adc_a_reg1_10" INST "adc_a_reg1_11" INST "adc_a_reg1_12" INST "adc_a_reg1_13" 
INST "adc_b_reg1_0" INST "adc_b_reg1_1" INST "adc_b_reg1_2" INST "adc_b_reg1_3" 
INST "adc_b_reg1_4" INST "adc_b_reg1_5" INST "adc_b_reg1_6" INST "adc_b_reg1_7" 
INST "adc_b_reg1_8" INST "adc_b_reg1_9" INST "adc_b_reg1_10" INST 
"adc_b_reg1_11" INST "adc_b_reg1_12" INST "adc_b_reg1_13" INST "adc_ovf_a_reg1" 
INST "adc_ovf_b_reg1";
+
+TIMEGRP "ADC_DATA_GRP" OFFSET = IN 9 ns VALID 4 ns BEFORE "clk_fpga_p" TIMEGRP 
"ADC_REG_GRP" RISING;
+
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