[Commit-gnuradio] r8712 - usrp2/trunk/fpga/top/u2_core

[matt]

Author: matt
Date: 2008-06-25 17:21:17 -0600 (Wed, 25 Jun 2008)
New Revision: 8712

Modified:
   usrp2/trunk/fpga/top/u2_core/u2_core.v
Log:
replaced crappy uart with a simple one, some debug pin changes as usual


Modified: usrp2/trunk/fpga/top/u2_core/u2_core.v
===================================================================
--- usrp2/trunk/fpga/top/u2_core/u2_core.v      2008-06-25 23:16:29 UTC (rev 
8711)
+++ usrp2/trunk/fpga/top/u2_core/u2_core.v      2008-06-25 23:21:17 UTC (rev 
8712)
@@ -140,7 +140,7 @@
    wire        ram_loader_rst, wb_rst, dsp_rst;
 
    wire [31:0]         status, status_b0, status_b1, status_b2, status_b3, 
status_b4, status_b5, status_b6, status_b7;
-   wire        bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, 
proc_int, overrun, underrun, uart_int;
+   wire        bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, 
proc_int, overrun, underrun, uart_tx_int, uart_rx_int;
 
    wire [31:0]         debug_gpio_0, debug_gpio_1;
    wire [31:0]         atr_lines;
@@ -441,7 +441,9 @@
    // /////////////////////////////////////////////////////////////////////////
    // Interrupt Controller, Slave #8
 
-   wire [8:0]   
irq={uart_int,pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int};
+   wire [8:0]   irq={{6'b0,uart_tx_int, uart_rx_int},
+                     
{pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}};
+   
    simple_pic #(.is(9),.dwidth(32)) simple_pic
      
(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]),
       
.we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int),
@@ -463,7 +465,7 @@
 
    // /////////////////////////////////////////////////////////////////////////
    // UART, Slave #10
-
+/*
    uart_top uart
      (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
       .wb_adr_i(s10_adr[4:0]),.wb_dat_i(s10_dat_o),.wb_dat_o(s10_dat_i),
@@ -472,7 +474,14 @@
       .stx_pad_o(uart_tx_o),.srx_pad_i(uart_rx_i),
       
.rts_pad_o(),.cts_pad_i(1'b0),.dtr_pad_o(),.dsr_pad_i(1'b0),.ri_pad_i(1'b0),.dcd_pad_i(1'b0),
       .baud_o(uart_baud_o) );
-
+*/
+   simple_uart uart
+     (.clk_i(wb_clk),.rst_i(wb_rst),
+      .we_i(s10_we),.stb_i(s10_stb),.cyc_i(s10_cyc),.ack_o(s10_ack),
+      .adr_i(s10_adr[4:2]),.dat_i(s10_dat_o),.dat_o(s10_dat_i),
+      .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int),
+      .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o));
+   
    assign       s10_err = 0;
    assign       s10_rty = 0;
    
@@ -603,15 +612,11 @@
                                 { ser_t[15:8] },
                                 { ser_t[7:0] } };
 
-   assign      debug_serdes1 = { 
{uart_tx_o,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write},
+   assign      debug_serdes1 = { 
{1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write},
                                 { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, 
ser_enable, ser_prbsen, ser_loopen, ser_rx_en },
                                 { ser_r[15:8] },
                                 { ser_r[7:0] } };
        
-   wire [31:0] debug_serdes_receiver = {uart_tx_o,debug_serdes2[30:0]};
-   wire [31:0] debug_serdes_sender = { uart_tx_o, debug_serdes0[30:0]};
-   wire [31:0] debug_serdes_common = debug_serdes1;
-   
    assign      debug_gpio_1 = {uart_tx_o,7'd0,
                               3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error,
                               debug_txc[15:0]};
@@ -625,8 +630,11 @@
    assign      debug_clk[0] = wb_clk;
    assign      debug_clk[1] = dsp_clk; 
    
-   assign      debug = {{strobe_rx,adc_ovf_a,adc_a},{run_rx,adc_ovf_b,adc_b}}; 
-   assign      debug_gpio_0 = 32'b0;
+   //   assign      debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a},
+   //                  {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}};
+
+   assign      debug = 0; // debug_serdes0;
+   assign      debug_gpio_0 = 0; // debug_serdes1;
    assign      debug_gpio_1 = 32'b0; 
    
 endmodule // u2_core