[Commit-gnuradio] r8723 - usrp2/trunk/fpga/control_lib

[matt]

Author: matt
Date: 2008-06-26 02:22:12 -0600 (Thu, 26 Jun 2008)
New Revision: 8723

Modified:
   usrp2/trunk/fpga/control_lib/simple_uart_rx.v
Log:
Seems to be working, need to check it on real hardware


Modified: usrp2/trunk/fpga/control_lib/simple_uart_rx.v
===================================================================
--- usrp2/trunk/fpga/control_lib/simple_uart_rx.v       2008-06-26 05:36:21 UTC 
(rev 8722)
+++ usrp2/trunk/fpga/control_lib/simple_uart_rx.v       2008-06-26 08:22:12 UTC 
(rev 8723)
@@ -6,12 +6,57 @@
      output [7:0] fifo_out, input fifo_read, output [7:0] fifo_level, output 
fifo_empty, 
      input [15:0] clkdiv, input rx);
 
-   wire          write, full;
-   wire [7:0]    rcvd_char;
+   reg                   rx_d1, rx_d2;
+   always @(posedge clk)
+     if(rst)
+       {rx_d2,rx_d1} <= 0;
+     else
+       {rx_d2,rx_d1} <= {rx_d1,rx};
    
+   wire          neg_trans = rx_d2 & ~rx_d1;
+   wire          shift_now = baud_ctr == (clkdiv>>1);
+   wire          stop_now = (bit_ctr == 10) && shift_now;
+   wire          go_now = (bit_ctr == 0) && neg_trans;
+   reg [15:0]    baud_ctr;
+   reg [3:0]     bit_ctr;
+   reg [7:0]     sr;
+   
+   always @(posedge clk)
+     if(rst)
+       sr <= 0;
+     else if(shift_now)
+       sr <= {rx_d2,sr[7:1]};
+   
+   always @(posedge clk)
+     if(rst)
+       baud_ctr <= 0;
+     else
+       if(go_now)
+        baud_ctr <= 1;
+       else if(stop_now)
+        baud_ctr <= 0;
+       else if(baud_ctr >= clkdiv)
+        baud_ctr <= 1;
+       else if(baud_ctr != 0)
+        baud_ctr <= baud_ctr + 1;
+
+   always @(posedge clk)
+     if(rst)
+       bit_ctr <= 0;
+     else 
+       if(go_now)
+        bit_ctr <= 1;
+       else if(stop_now)
+        bit_ctr <= 0;
+       else if(baud_ctr == clkdiv)
+        bit_ctr <= bit_ctr + 1;
+   
+   wire          full;
+   wire          write = ~full & rx_d2 & stop_now;
+   
    medfifo #(.WIDTH(8),.DEPTH(DEPTH)) fifo
      (.clk(clk),.rst(rst),
-      .datain(rcvd_char),.write(write),.full(full),
+      .datain(sr),.write(write),.full(full),
       .dataout(fifo_out),.read(fifo_read),.empty(fifo_empty),
       .clear(0),.space(),.occupied(fifo_level[3:0]) );
    assign        fifo_level[7:4] = 0;