[Commit-gnuradio] r8730 - usrp2/trunk/fpga/control_lib

[matt]

Author: matt
Date: 2008-06-26 14:50:09 -0600 (Thu, 26 Jun 2008)
New Revision: 8730

Modified:
   usrp2/trunk/fpga/control_lib/medfifo.v
Log:
rearranged to appease the Xilinx gods


Modified: usrp2/trunk/fpga/control_lib/medfifo.v
===================================================================
--- usrp2/trunk/fpga/control_lib/medfifo.v      2008-06-26 20:39:01 UTC (rev 
8729)
+++ usrp2/trunk/fpga/control_lib/medfifo.v      2008-06-26 20:50:09 UTC (rev 
8730)
@@ -1,61 +1,46 @@
 
 module medfifo
   #(parameter WIDTH=32,
-    parameter DEPTH=0)
+    parameter DEPTH=1)
     (input clk, input rst,
      input [WIDTH-1:0] datain,
-     output reg [WIDTH-1:0] dataout,
+     output [WIDTH-1:0] dataout,
      input read,
      input write,
      input clear,
-     output reg full,
-     output reg empty,
+     output full,
+     output empty,
      output [3:0] space,
      output [3:0] occupied);
 
    localparam          NUM_FIFOS = (1<<DEPTH);
    
-   reg [WIDTH-1:0]     din [0:NUM_FIFOS-1];
    wire [WIDTH-1:0]    dout [0:NUM_FIFOS-1];
-   reg                         wr [0:NUM_FIFOS-1];
-   reg                         rd [0:NUM_FIFOS-1];
-   wire                full_x [0:NUM_FIFOS-1];
-   wire                empty_x [0:NUM_FIFOS-1];
-   wire [3:0]          space_x [0:NUM_FIFOS-1];
-   wire [3:0]          occupied_x [0:NUM_FIFOS-1];
+   wire [0:NUM_FIFOS-1] full_x;
+   wire [0:NUM_FIFOS-1] empty_x;
+
+   shortfifo #(.WIDTH(WIDTH))
+     head (.clk(clk),.rst(rst),
+          .datain(datain),.write(write),.full(full),
+          .dataout(dout[0]),.read(~empty_x[0] & ~full_x[1]),.empty(empty_x[0]),
+          .clear(clear),.space(space),.occupied() );
    
+   shortfifo #(.WIDTH(WIDTH))
+     tail (.clk(clk),.rst(rst),
+          .datain(dout[NUM_FIFOS-2]),.write(~empty_x[NUM_FIFOS-2] & 
~full_x[NUM_FIFOS-1]),.full(full_x[NUM_FIFOS-1]),
+          .dataout(dataout),.read(read),.empty(empty),
+          .clear(clear),.space(),.occupied(occupied) );
+
    genvar              i;
    generate
-      for(i = 0; i < NUM_FIFOS ; i = i + 1)
+      for(i = 1; i < NUM_FIFOS-1 ; i = i + 1)
        begin : gen_depth
           shortfifo #(.WIDTH(WIDTH))
             shortfifo (.clk(clk),.rst(rst),
-                       .datain(din[i]),.write(wr[i]),.full(full_x[i]),
-                       .dataout(dout[i]),.read(rd[i]),.empty(empty_x[i]),
-                       
.clear(clear),.space(space_x[i]),.occupied(occupied_x[i]) );
+                       .datain(dout[i-1]),.write(~full_x[i] & 
~empty_x[i-1]),.full(full_x[i]),
+                       .dataout(dout[i]),.read(~full_x[i+1] & 
~empty_x[i]),.empty(empty_x[i]),
+                       .clear(clear),.space(),.occupied() );
        end
    endgenerate
 
-   integer j;
-   always @*
-     begin
-       din[0] = datain;
-       wr[0] = write;
-       full = full_x[0];
-       
-       for(j = 1; j < NUM_FIFOS; j = j + 1)
-         begin
-            din[j] = dout[j-1];
-            wr[j] = ~full_x[j] & ~empty_x[j-1];
-            rd[j-1] = ~full_x[j] & ~empty_x[j-1];
-         end
-
-       dataout = dout[NUM_FIFOS-1];
-       rd[NUM_FIFOS-1] = read;
-       empty = empty_x[NUM_FIFOS-1];
-     end // always @ *
-
-   assign space = space_x[0];
-   assign occupied = occupied_x[NUM_FIFOS-1];
-   
 endmodule // medfifo