[Commit-gnuradio] r8736 - usrp2/trunk/fpga/top/u2_rev2

[matt]

Author: matt
Date: 2008-06-26 22:29:07 -0600 (Thu, 26 Jun 2008)
New Revision: 8736

Modified:
   usrp2/trunk/fpga/top/u2_rev2/Makefile
Log:
remove old uart


Modified: usrp2/trunk/fpga/top/u2_rev2/Makefile
===================================================================
--- usrp2/trunk/fpga/top/u2_rev2/Makefile       2008-06-27 01:12:22 UTC (rev 
8735)
+++ usrp2/trunk/fpga/top/u2_rev2/Makefile       2008-06-27 04:29:07 UTC (rev 
8736)
@@ -133,18 +133,6 @@
 opencores/spi/rtl/verilog/spi_shift.v \
 opencores/spi/rtl/verilog/spi_top.v \
 opencores/spi/rtl/verilog/timescale.v \
-opencores/uart16550/rtl/verilog/raminfr.v \
-opencores/uart16550/rtl/verilog/timescale.v \
-opencores/uart16550/rtl/verilog/uart_debug_if.v \
-opencores/uart16550/rtl/verilog/uart_defines.v \
-opencores/uart16550/rtl/verilog/uart_receiver.v \
-opencores/uart16550/rtl/verilog/uart_regs.v \
-opencores/uart16550/rtl/verilog/uart_rfifo.v \
-opencores/uart16550/rtl/verilog/uart_sync_flops.v \
-opencores/uart16550/rtl/verilog/uart_tfifo.v \
-opencores/uart16550/rtl/verilog/uart_top.v \
-opencores/uart16550/rtl/verilog/uart_transmitter.v \
-opencores/uart16550/rtl/verilog/uart_wb.v \
 sdr_lib/acc.v \
 sdr_lib/add2.v \
 sdr_lib/add2_and_round.v \