[Commit-gnuradio] r8752 - usrp2/trunk/fpga/sdr_lib

[matt]

Author: matt
Date: 2008-06-30 13:24:49 -0600 (Mon, 30 Jun 2008)
New Revision: 8752

Modified:
   usrp2/trunk/fpga/sdr_lib/cic_decim.v
   usrp2/trunk/fpga/sdr_lib/cic_interp.v
   usrp2/trunk/fpga/sdr_lib/rx_dcoffset.v
Log:
remove #1 delays, archaic style


Modified: usrp2/trunk/fpga/sdr_lib/cic_decim.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/cic_decim.v        2008-06-30 05:15:55 UTC (rev 
8751)
+++ usrp2/trunk/fpga/sdr_lib/cic_decim.v        2008-06-30 19:24:49 UTC (rev 
8752)
@@ -47,33 +47,33 @@
    always @(posedge clock)
      if(reset)
        for(i=0;i<N;i=i+1)
-        integrator[i] <= #1 0;
+        integrator[i] <= 0;
      else if (enable && strobe_in)
        begin
-         integrator[0] <= #1 integrator[0] + signal_in_ext;
+         integrator[0] <= integrator[0] + signal_in_ext;
          for(i=1;i<N;i=i+1)
-           integrator[i] <= #1 integrator[i] + integrator[i-1];
+           integrator[i] <= integrator[i] + integrator[i-1];
        end     
    
    always @(posedge clock)
      if(reset)
        begin
-         sampler <= #1 0;
+         sampler <= 0;
          for(i=0;i<N;i=i+1)
            begin
-              pipeline[i] <= #1 0;
-              differentiator[i] <= #1 0;
+              pipeline[i] <= 0;
+              differentiator[i] <= 0;
            end
        end
      else if (enable && strobe_out)
        begin
-         sampler <= #1 integrator[N-1];
-         differentiator[0] <= #1 sampler;
-         pipeline[0] <= #1 sampler - differentiator[0];
+         sampler <= integrator[N-1];
+         differentiator[0] <= sampler;
+         pipeline[0] <= sampler - differentiator[0];
          for(i=1;i<N;i=i+1)
            begin
-              differentiator[i] <= #1 pipeline[i-1];
-              pipeline[i] <= #1 pipeline[i-1] - differentiator[i];
+              differentiator[i] <= pipeline[i-1];
+              pipeline[i] <= pipeline[i-1] - differentiator[i];
            end
        end // if (enable && strobe_out)
    

Modified: usrp2/trunk/fpga/sdr_lib/cic_interp.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/cic_interp.v       2008-06-30 05:15:55 UTC (rev 
8751)
+++ usrp2/trunk/fpga/sdr_lib/cic_interp.v       2008-06-30 19:24:49 UTC (rev 
8752)
@@ -47,13 +47,13 @@
    always @(posedge clock)
      if(reset | ~enable)
        for(i=0;i<N;i=i+1)
-        integrator[i] <= #1 0;
+        integrator[i] <= 0;
      else if (enable & strobe_out)
        begin
          if(strobe_in)
-           integrator[0] <= #1 integrator[0] + pipeline[N-1];
+           integrator[0] <= integrator[0] + pipeline[N-1];
          for(i=1;i<N;i=i+1)
-           integrator[i] <= #1 integrator[i] + integrator[i-1];
+           integrator[i] <= integrator[i] + integrator[i-1];
        end
    
    always @(posedge clock)
@@ -61,18 +61,18 @@
        begin
          for(i=0;i<N;i=i+1)
            begin
-              differentiator[i] <= #1 0;
-              pipeline[i] <= #1 0;
+              differentiator[i] <= 0;
+              pipeline[i] <= 0;
            end
        end
      else if (enable && strobe_in)
        begin
-         differentiator[0] <= #1 signal_in_ext;
-         pipeline[0] <= #1 signal_in_ext - differentiator[0];
+         differentiator[0] <= signal_in_ext;
+         pipeline[0] <= signal_in_ext - differentiator[0];
          for(i=1;i<N;i=i+1)
            begin
-              differentiator[i] <= #1 pipeline[i-1];
-              pipeline[i] <= #1 pipeline[i-1] - differentiator[i];
+              differentiator[i] <= pipeline[i-1];
+              pipeline[i] <= pipeline[i-1] - differentiator[i];
            end
        end
 

Modified: usrp2/trunk/fpga/sdr_lib/rx_dcoffset.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/rx_dcoffset.v      2008-06-30 05:15:55 UTC (rev 
8751)
+++ usrp2/trunk/fpga/sdr_lib/rx_dcoffset.v      2008-06-30 19:24:49 UTC (rev 
8752)
@@ -18,11 +18,11 @@
    
    always @(posedge clk)
      if(rst)
-       integrator <= #1 32'd0;
+       integrator <= 32'd0;
      else if(set_now)
-       integrator <= #1 {set_data[WIDTH-1:0],{(32-WIDTH){1'b0}}};
+       integrator <= {set_data[WIDTH-1:0],{(32-WIDTH){1'b0}}};
      else if(~fixed)
-       integrator <= #1 integrator + adc_out;
+       integrator <= integrator + adc_out;
    
    wire [WIDTH:0]      scaled_integrator = 
{integrator[31],(integrator[31:32-WIDTH] + (integrator[31] & 
|integrator[31-WIDTH:0]))};
    wire [WIDTH:0]      adc_out_int = {adc_in[WIDTH-1],adc_in} - 
scaled_integrator;