[Commit-gnuradio] r8756 - usrp2/trunk/fpga/top/u2_rev2

[matt]

Author: matt
Date: 2008-06-30 17:14:33 -0600 (Mon, 30 Jun 2008)
New Revision: 8756

Modified:
   usrp2/trunk/fpga/top/u2_rev2/u2_rev2.ucf
   usrp2/trunk/fpga/top/u2_rev2/u2_rev2.v
Log:
experimental changes to fix timing


Modified: usrp2/trunk/fpga/top/u2_rev2/u2_rev2.ucf
===================================================================
--- usrp2/trunk/fpga/top/u2_rev2/u2_rev2.ucf    2008-06-30 21:37:06 UTC (rev 
8755)
+++ usrp2/trunk/fpga/top/u2_rev2/u2_rev2.ucf    2008-06-30 23:14:33 UTC (rev 
8756)
@@ -308,9 +308,12 @@
 NET "clk_to_mac" TNM_NET = "clk_to_mac";
 TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
 
-NET "dsp_clk" TNM_NET = "dsp_clk";
-TIMESPEC "TS_dsp_clk" = PERIOD "dsp_clk" 10 ns HIGH 50 %;
+#NET "dsp_clk" TNM_NET = "dsp_clk";
+#TIMESPEC "TS_dsp_clk" = PERIOD "dsp_clk" 10 ns HIGH 50 %;
 
+NET "clk_fpga_p" TNM_NET = "clk_fpga_p";
+TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %;
+
 NET "cpld_clk" TNM_NET = "cpld_clk";
 TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
 
@@ -320,45 +323,15 @@
 NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
 TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
 
-NET "wb_clk" TNM_NET = "wb_clk";
-TIMESPEC "TS_wb_clk" = PERIOD "wb_clk" 20 ns HIGH 50 %;
+#NET "wb_clk" TNM_NET = "wb_clk";
+#TIMESPEC "TS_wb_clk" = PERIOD "wb_clk" 20 ns HIGH 50 %;
 
-
 NET "GMII_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE; 
 NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE;
-INST "adc_a<0>" TNM = ADC_DATA_GRP;
-INST "adc_a<1>" TNM = ADC_DATA_GRP;
-INST "adc_a<2>" TNM = ADC_DATA_GRP;
-INST "adc_a<3>" TNM = ADC_DATA_GRP;
-INST "adc_a<4>" TNM = ADC_DATA_GRP;
-INST "adc_a<5>" TNM = ADC_DATA_GRP;
-INST "adc_a<6>" TNM = ADC_DATA_GRP;
-INST "adc_a<7>" TNM = ADC_DATA_GRP;
-INST "adc_a<8>" TNM = ADC_DATA_GRP;
-INST "adc_a<9>" TNM = ADC_DATA_GRP;
-INST "adc_a<10>" TNM = ADC_DATA_GRP;
-INST "adc_a<11>" TNM = ADC_DATA_GRP;
-INST "adc_a<12>" TNM = ADC_DATA_GRP;
-INST "adc_a<13>" TNM = ADC_DATA_GRP;
-INST "adc_b<0>" TNM = ADC_DATA_GRP;
-INST "adc_b<1>" TNM = ADC_DATA_GRP;
-INST "adc_b<2>" TNM = ADC_DATA_GRP;
-INST "adc_b<3>" TNM = ADC_DATA_GRP;
-INST "adc_b<4>" TNM = ADC_DATA_GRP;
-INST "adc_b<5>" TNM = ADC_DATA_GRP;
-INST "adc_b<6>" TNM = ADC_DATA_GRP;
-INST "adc_b<7>" TNM = ADC_DATA_GRP;
-INST "adc_b<8>" TNM = ADC_DATA_GRP;
-INST "adc_b<9>" TNM = ADC_DATA_GRP;
-INST "adc_b<10>" TNM = ADC_DATA_GRP;
-INST "adc_b<11>" TNM = ADC_DATA_GRP;
-INST "adc_b<12>" TNM = ADC_DATA_GRP;
-INST "adc_b<13>" TNM = ADC_DATA_GRP;
-INST "adc_ovf_a" TNM = ADC_DATA_GRP;
-INST "adc_ovf_b" TNM = ADC_DATA_GRP;
 
+NET "adc_a<*>" TNM_NET = ADC_DATA_GRP;
+NET "adc_b<*>" TNM_NET = ADC_DATA_GRP;
+TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
 
-TIMEGRP "ADC_REG_GRP" = INST "adc_a_reg1_0" INST "adc_a_reg1_1" INST 
"adc_a_reg1_2" INST "adc_a_reg1_3" INST "adc_a_reg1_4" INST "adc_a_reg1_5" INST 
"adc_a_reg1_6" INST "adc_a_reg1_7" INST "adc_a_reg1_8" INST "adc_a_reg1_9" INST 
"adc_a_reg1_10" INST "adc_a_reg1_11" INST "adc_a_reg1_12" INST "adc_a_reg1_13" 
INST "adc_b_reg1_0" INST "adc_b_reg1_1" INST "adc_b_reg1_2" INST "adc_b_reg1_3" 
INST "adc_b_reg1_4" INST "adc_b_reg1_5" INST "adc_b_reg1_6" INST "adc_b_reg1_7" 
INST "adc_b_reg1_8" INST "adc_b_reg1_9" INST "adc_b_reg1_10" INST 
"adc_b_reg1_11" INST "adc_b_reg1_12" INST "adc_b_reg1_13" INST "adc_ovf_a_reg1" 
INST "adc_ovf_b_reg1";
-
-TIMEGRP "ADC_DATA_GRP" OFFSET = IN 9 ns VALID 4 ns BEFORE "clk_fpga_p" TIMEGRP 
"ADC_REG_GRP" RISING;
-
+#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
+#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;

Modified: usrp2/trunk/fpga/top/u2_rev2/u2_rev2.v
===================================================================
--- usrp2/trunk/fpga/top/u2_rev2/u2_rev2.v      2008-06-30 21:37:06 UTC (rev 
8755)
+++ usrp2/trunk/fpga/top/u2_rev2/u2_rev2.v      2008-06-30 23:14:33 UTC (rev 
8756)
@@ -154,6 +154,7 @@
    assign      cpld_init_b = 0;
    // FPGA-specific pins connections
    wire        clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;
+   wire        clk90, clk180, clk270;
 
    IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
    defparam    clk_fpga_pin.IOSTANDARD = "LVPECL_25";
@@ -180,7 +181,7 @@
    reg [13:0]   adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;
    reg                  adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, 
adc_ovf_b_reg2;
 
-   always @(posedge dsp_clk)
+   always @(posedge clk90)
      begin
        adc_a_reg1 <= adc_a;
        adc_b_reg1 <= adc_b;
@@ -210,9 +211,9 @@
                  .CLK0(dcm_out), 
                  .CLK2X(), 
                  .CLK2X180(), 
-                 .CLK90(), 
-                 .CLK180(), 
-                 .CLK270(), 
+                 .CLK90(clk90), 
+                 .CLK180(clk180), 
+                 .CLK270(clk270), 
                  .LOCKED(LOCKED_OUT), 
                  .PSDONE(), 
                  .STATUS());