[Commit-gnuradio] r8821 - usrp2/trunk/fpga/sdr_lib

[matt]

Author: matt
Date: 2008-07-07 19:44:46 -0600 (Mon, 07 Jul 2008)
New Revision: 8821

Modified:
   usrp2/trunk/fpga/sdr_lib/small_hb_int.v
Log:
seems to work now


Modified: usrp2/trunk/fpga/sdr_lib/small_hb_int.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/small_hb_int.v     2008-07-08 01:44:30 UTC (rev 
8820)
+++ usrp2/trunk/fpga/sdr_lib/small_hb_int.v     2008-07-08 01:44:46 UTC (rev 
8821)
@@ -3,6 +3,7 @@
 //
 // These taps designed by halfgen4 from ldoolittle:
 //   2 * 131072 * halfgen4(.75/8,2)
+
 module small_hb_int
   #(parameter WIDTH=18)
     (input clk,
@@ -10,24 +11,30 @@
      input bypass,
      input stb_in,
      input [WIDTH-1:0] data_in,
-     output reg stb_out,
+     input [7:0] output_rate,
+     input stb_out,
      output reg [WIDTH-1:0] data_out);
 
-   reg [WIDTH-1:0] filt_out;
-   reg                    filt_out_stb;
-   reg                    odd;
-   reg [WIDTH-1:0] d1, d2, d3, d4;
+   reg                    phase;
+   reg [WIDTH-1:0] d1, d2, d3, d4, d5, d6;
 
    localparam     MWIDTH = 36;
    wire [MWIDTH-1:0] prod;
+
+   reg [6:0]        stbin_d;
    
    always @(posedge clk)
+     stbin_d <= {stbin_d[5:0],stb_in};
+   
+   always @(posedge clk)
      if(stb_in)
        begin
          d1 <= data_in;
          d2 <= d1;
          d3 <= d2;
          d4 <= d3;
+         d5 <= d4;
+         d6 <= d5;
        end
 
    wire [WIDTH-1:0] sum_outer, sum_inner;
@@ -36,39 +43,43 @@
 
    wire [17:0]            coeff_outer = -10690;
    wire [17:0]            coeff_inner = 75809;
-   reg                    phase = 0;
-   MULT18X18S mult(.C(clk), .CE(1), .R(rst), .P(prod), .A(phase ? coeff_outer 
: coeff_inner), .B(phase ? sum_outer : sum_inner) );
 
+   MULT18X18S mult(.C(clk), .CE(1), .R(rst), .P(prod), .A(stbin_d[1] ? 
coeff_outer : coeff_inner), 
+                  .B(stbin_d[1] ? sum_outer : sum_inner) );
+
    wire [MWIDTH:0] accum;
    acc #(.IWIDTH(MWIDTH),.OWIDTH(MWIDTH+1)) 
-     acc (.clk(clk),.clear(),.acc(),.in(prod),.out(accum));
+     acc 
(.clk(clk),.clear(stbin_d[2]),.acc(|stbin_d[3:2]),.in(prod),.out(accum));
    
-   wire [17:0]          accum_rnd;
-   round_reg #(.bits_in(MWIDTH+1),.bits_out(WIDTH))
+   wire [WIDTH+2:0]     accum_rnd;
+   round_reg #(.bits_in(MWIDTH+1),.bits_out(WIDTH+3))
      final_round (.clk(clk),.in(accum),.out(accum_rnd));
 
+   wire [WIDTH-1:0]     clipped;
+   clip_reg #(.bits_in(WIDTH+3),.bits_out(WIDTH))
+     final_clip (.clk(clk),.in(accum_rnd),.out(clipped));
+
+   reg [WIDTH-1:0]      saved, saved_d3;
    always @(posedge clk)
-     filt_out <= phase ? accum_rnd : d3;
-   
-   always @(posedge clk)
-     if(rst)
-       odd <= 0;
-     else if(stb_out)
-       odd <= ~odd;
+     if(stbin_d[6])
+       saved <= clipped;
 
    always @(posedge clk)
-     if(bypass)
+     if(stbin_d[3])
+       saved_d3 <= d3;
+          
+   always @(posedge clk)
+     if(bypass && stb_out)
        data_out <= data_in;
-     else
-       data_out <= filt_out;
+     else if(stb_in & stb_out)
+       case(output_rate)
+        1 : data_out <= d6; 
+        2 : data_out <= d4;
+        3, 4, 5, 6, 7 : data_out <= d3;
+        default : data_out <= d2;
+       endcase // case(output_rate)
+     else if(stb_out)
+       data_out <= saved;
 
-   always @(posedge clk)
-     if(bypass)
-       stb_out <= stb_in;
-     else
-       stb_out <= filt_out_stb;
-
-   
-
 endmodule // small_hb_int