[Commit-gnuradio] r8894 - in usrp2/trunk/fpga: coregen eth eth/rtl/verilog top/u2_core

[matt]

Author: matt
Date: 2008-07-15 17:44:44 -0600 (Tue, 15 Jul 2008)
New Revision: 8894

Added:
   usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.asy
   usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.ngc
   usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.sym
   usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.v
   usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.veo
   usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.vhd
   usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.vho
   usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.xco
   usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso
   
usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
   usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk_flist.txt
   usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk_readme.txt
   usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl
Modified:
   usrp2/trunk/fpga/eth/mac_txfifo_int.v
   usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v
   usrp2/trunk/fpga/top/u2_core/u2_core.v
Log:
moved clock-domain crossing out of ethernet core because either the original 
code is bad, or xilinx can't synthesize it properly.  This wastes a block ram 
because there are now 2 fifos, but it gets rid of the intermittent bad packets 
we were seeing.


Added: usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.asy
===================================================================
--- usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.asy                          
(rev 0)
+++ usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.asy  2008-07-15 23:44:44 UTC 
(rev 8894)
@@ -0,0 +1,41 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 fifo_xlnx_512x36_2clk
+RECTANGLE Normal 32 32 544 672
+LINE Wide 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName din[35:0]
+PINATTR Polarity IN
+LINE Normal 0 144 32 144
+PIN 0 144 LEFT 36
+PINATTR PinName wr_en
+PINATTR Polarity IN
+LINE Normal 0 176 32 176
+PIN 0 176 LEFT 36
+PINATTR PinName wr_clk
+PINATTR Polarity IN
+LINE Normal 0 240 32 240
+PIN 0 240 LEFT 36
+PINATTR PinName rd_en
+PINATTR Polarity IN
+LINE Normal 0 272 32 272
+PIN 0 272 LEFT 36
+PINATTR PinName rd_clk
+PINATTR Polarity IN
+LINE Normal 144 704 144 672
+PIN 144 704 BOTTOM 36
+PINATTR PinName rst
+PINATTR Polarity IN
+LINE Wide 576 80 544 80
+PIN 576 80 RIGHT 36
+PINATTR PinName dout[35:0]
+PINATTR Polarity OUT
+LINE Normal 576 208 544 208
+PIN 576 208 RIGHT 36
+PINATTR PinName full
+PINATTR Polarity OUT
+LINE Normal 576 432 544 432
+PIN 576 432 RIGHT 36
+PINATTR PinName empty
+PINATTR Polarity OUT
+

Added: usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.ngc
===================================================================
--- usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.ngc                          
(rev 0)
+++ usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.ngc  2008-07-15 23:44:44 UTC 
(rev 8894)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.4e
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;j7}|`g^dvhiYs`{oxdR`jg`vf,0/6i2zycjQiumn\pmtb{aUeijo{e)4*5d=wzfmTjxbc_ujqavnXflmjxh&8)0c8twi`Wog`Rzgrdqk[kc`i}o#4$?l;qplcZ`rdeUdk|h^lfcdrb410;2;5}d^aoo46<zmUomyoPcnwmp-6.991yhRjnt`]`kphs
 
8#:<6|k_ecweZeh}g~#>$??;sf\`drfWje~by&<)028vaYci}kTob{at)6*55=ulVnjxlQlotlw,0/682xoSio{a^alqkr/>
 
;;7jPd`vb[firf}"<%<>4re]geqgXkfex%6&119q`Zbf|hUhcx`{<1<26>tcWmkmRm`uov?<?69=2xoSh`9;sf\vvr43{y;6}miugqv1=tzz~9=6zbp.]`c*`nnfUs`cvP500{73Y5kea%bja;;upva<=rfmoyjaax5:tbhlb13~xTmne9;vp\gim682}ySio{a^alqkr/8
 
;;7z|Pd`vb[firf}":%<>4ws]geqgXkfex%<&119tvZbf|hUhcx`{(2+24>quWmkmRm`uov+0,773~xThlzn_bmvjq.2!8:0{Qkauc\gjsi|!<"==5xr^fbpdYdg|d$:'>0:uq[agsiVidycz'8(31?rtXlh~jSnaznu>;>5823~xTic84ws]qwq{GHyh:m6NOx5d`>C<328qX8o4;a386>455>1>j6>6l5bym7cc=92d8jk4;;%1eg?5a>2wX844;a386>455>1>j6>6l5b9P513=<hh1<7?<27:7e?5?k<n0_9754``94?74:?2?m7=7c4g8`1g2290:6<u\4c87e7<22899:5:n:2:`1f=q\8km6=4>:082<0}T<k0?m?4::0112=2f2:2h9n5+3g29510<^:lo6?uz15d95>s6=90;7p*>a68e?g2f=3:18k4<:5dxL6cb3S>;6?uk:b8~
 
4d32=k>7)=ib;6b0>o3n>0;66g:0b83>>i3i00;66a;a283>>o2880;66g;f883>>i3??0;6)?n9;6:=>h6i10;76a;7483>!7f13>256`>a982?>i3?=0;6)?n9;6:=>h6i10976a;7283>!7f13>256`>a980?>i3?;0;6)?n9;6:=>h6i10?76a;7083>!7f13>256`>a986?>i3>o0;6)?n9;6:=>h6i10=76a;6d83>!7f13>256`>a984?>i3>m0;6)?n9;6:=>h6i10376a;6b83>!7f13>256`>a98:?>i3>k0;6)?n9;6:=>h6i10j76a;6`83>!7f13>256`>a98a?>i3>00;6)?n9;6:=>h6i10h76a;6983>!7f13>256`>a98g?>i3>>0;6)?n9;6:=>h6i10n76a;6783>!7f13>256`>a98e?>i3>=0;6)?n9;6:=>h6i10:<65`47194?"6i00?545a1`:954=<g=<96=4+1`;90<?<f8k36<<4;n655?6=,8k26976;o3b<?7432e?:=4?:%3b=?2>12d:m54>4:9l00`=83.:m44;989m5d>=9<10c9;j:18'5d?=<030b<o7:048?j22l3:1(<o6:5;:?k7f03;<76a;5b83>!7f13>256`>a982<>=h<<h1<7*>a887=<=i9h21=454o55`>5<#9h318474n0c;>4g<3f><n7>5$0c:>1?>3g;j47?m;:m73d<72-;j57:69:l2e=<6k21d8:750;&2e<<3101e=l651e98k11?290/=l7548;8j4g?28o07b:87;29
 
4g>2=327c?n8;3e?>i3?90;6)?n9;6:=>h6i109<65`47794?"6i00?545a1`:964=<g=?j6=4+1`;90<?<f8k36?<4;n66=?6=,8k26976;o3b<?4432c?>i4?:%3b=?2282d:m54?;:k76f<72-;j57::0:l2e=<632c?>o4?:%3b=?2282d:m54=;:k76d<72-;j57::0:l2e=<432c?>44?:%3b=?2282d:m54;;:k76=<72-;j57::0:l2e=<232c?>;4?:%3b=?2282d:m549;:k760<72-;j57::0:l2e=<032c?>94?:%3b=?2282d:m547;:k766<72-;j57::0:l2e=<>32c?>?4?:%3b=?2282d:m54n;:k764<72-;j57::0:l2e=<e32c?>=4?:%3b=?2282d:m54l;:k75c<72-;j57::0:l2e=<c32c?=h4?:%3b=?2282d:m54j;:k75a<72-;j57::0:l2e=<a32c?=o4?:%3b=?2282d:m54>0:9j04g=83.:m44;519m5d>=9810e9?6:18'5d?=<<:0b<o7:008?l2603:1(<o6:573?k7f03;876g;1683>!7f13>><6`>a9820>=n<8<1<7*>a88715=i9h21=854i536>5<#9h3188>4n0c;>40<3`>:87>5$0c:>1373g;j47?8;:k756<72-;j57::0:l2e=<6021b8<<50;&2e<<3=91e=l651898m154290/=l754428j4g?28k07d:<2;29
 
4g>2=?;7c?n8;3a?>o3;80;6)?n9;664>h6i10:o65f42294?"6i00?9=5a1`:95a=<a=8m6=4+1`;9006<f8k36<k4;h61a?6=,8k269;?;o3b<?7a32c?>:4?:%3b=?2282d:m54=0:9j04e=83.:m44;519m5d>=:810e9?>:18'5d?=<<:0b<o7:308?l2683:1(<o6:573?k7f038876g;ec83>>d4mo0;6<4?:1yK7`c<,8h?6>ki;n3b2?6=3thm>7>51;294~N4ml1/=o:5f39lb4<722wi?k4?:c3956?=91?pD>kj;[63>40|:;0957<7:34962<5<3n1><4l:37966<5?3826i4=8;01>f<5>38>6?:522815?{#9k>18l64$061>c6<,=>18l84$5c90d1<,8k:6<o:;h6e<?6=3f>ho7>5;h6ef?6=3f>;<7>5;n6eb?6=3`>;?7>5;h6`4?6=,8k269m>;o3b<?6<3`>ij7>5$0c:>1e63g;j47?4;h6aa?6=,8k269m>;o3b<?4<3`>ih7>5$0c:>1e63g;j47=4;h6ag?6=,8k269m>;o3b<?2<3`>in7>5$0c:>1e63g;j47;4;h6ae?6=,8k269m>;o3b<?0<3`>i57>5$0c:>1e63g;j4794;h6a<?6=,8k269m>;o3b<?><3`>m;7>5;n6bg?6=3f?;m7>5$0c:>06e3g;j47>4;n73=?6=,8k268>m;o3b<?7<3f?;47>5$0c:>06e3g;j47<4;n733?6=,8k268>m;o3b<?5<3f?;:7>5$0c:>06e3g;j47:4;n731?6=,8k268>m;o3b<?3<3f?;87>5$0c:>06e3g;j4784;n737?6=,8k268>m;o3b<?1<3f?;>7>5$0c:>06e3g;j4764;n6e0?6=,8k269h9;o3b<?6<3f>m?7>5$0c:>1`13g;j47?4;n6e6?6=,8k269h9;o3b<?4<3f>m=7>5$0c:>1`13g;j47=4;n6e4?6=,8k269h9;o3b<?2<3f>nj7>5$0c:>1`13g;j47;4;n6fa?6=,8k269h9;o3b<?0<3f>nh7>5$0c:>1`13g;j4794;n6fg?6=,8k269h9;o3b<?><3`>n57>5$0c:>1cf3g;j47>4;h6f<?6=,8k269kn;o3b<?7<3`>n;7>5$0c:>1cf3g;j47<4;h6f2?6=,8k269kn;o3b<?5<3`>n97>5$0c:>1cf3g;j47:4;h6f0?6=,8k269kn;o3b<?3<3`>n?7>5$0c:>1cf3g;j4784;h6f6?6=,8k269kn;o3b<?1<3`>n=7>5$0c:>1cf3g;j4764;h73g?6=3f>;h7>5$0c:>16b3g;j47>4;n63g?6=,8k269>j;o3b<?7<3f>;n7>5$0c:>16b3g;j47<4;n63e?6=,8k269>j;o3b<?5<3f>;57>5$0c:>16b3g;j47:4;n63<?6=,8k269>j;o3b<?3<3f>;;7>5$0c:>16b3g;j4784;n632?6=,8k269>j;o3b<?1<3f>;97>5$0c:>16b3g;j4764;n6b=?6=3f>j?7>5;h6g1?6=,8k269j9;o3b<?6<3`>o87>5$0c:>1b13g;j47?4;h6g7?6=,8k269j9;o3b<?4<3`>o>7>5$0c:>1b13g;j47=4;h6g5?6=,8k269j9;o3b<?2<3`>o<7>5$0c:>1b13g;j47;4;h6`b?6=,8k269j9;o3b<?0<3`>hi7>5$0c:>1b13g;j4794;h6``?6=,8k269j9;o3b<?><3`?;=7>5;h6be?6=3`>;87>5;h73`?6=3f>mm7>5;n734?6=3f>;=7>5;n6ea?6=3`>m57>5;n642?6=,8k26976;o3b<?6<3f><97>5$0c:>1?>3g;j47?4;n640?6=,8k26976;o3b<?4<3f><?7>5$0c:>1?>3g;j47=4;n646?6=,8k26976;o3b<?2<3f><=7>5$0c:>1?>3g;j47;4;n65b?6=,8k26976;o3b<?0<3f>=i7>5$0c:>1?>3g;j4794;n65`?6=,8k26976;o3b<?><3f>=o7>5$0c:>1?>3g;j4774;n65f?6=,8k26976;o3b<?g<3f>=m7>5$0c:>1?>3g;j47l4;n65=?6=,8k26976;o3b<?e<3f>=47>5$0c:>1?>3g;j47j4;n653?6=,8k26976;o3b<?c<3f>=:7>5$0c:>1?>3g;j47h4;n650?6=,8k26976;o3b<?7732e?:>4?:%3b=?2>12d:m54>1:9l034=83.:m44;989m5d>=9;10c98>:18'5d?=<030b<o7:018?j2183:1(<o6:5;:?k7f03;?76a;5g83>!7f13>256`>a9821>=h<<o1<7*>a887=<=i9h21=;54o57g>5<#9h318474n0c;>41<3f>>o7>5$0c:>1?>3g;j47?7;:m71g<72-;j57:69:l2e=<6121d8:m50;&2e<<3101e=l651`98k11e290/=l7548;8j4g?28h07b:8a;29
 
4g>2=327c?n8;3`?>i3?00;6)?n9;6:=>h6i10:h65`46:94?"6i00?545a1`:95`=<g==<6=4+1`;90<?<f8k36<h4;n644?6=,8k26976;o3b<?4732e?:84?:%3b=?2>12d:m54=1:9l00g=83.:m44;989m5d>=:;10c9;6:18'5d?=<030b<o7:318?l2e>3:1(<o6:5`4?k7f03:07d:m5;29
 4g>2=h<7c?n8;38?l2e<3:1(<o6:5`4?k7f03807d:m3;29 
4g>2=h<7c?n8;18?l2e:3:1(<o6:5`4?k7f03>07d:m1;29 
4g>2=h<7c?n8;78?l2e83:1(<o6:5`4?k7f03<07d:nf;29 
4g>2=h<7c?n8;58?l2fm3:1(<o6:5`4?k7f03207d:=d;29 
4g>2=?;7c?n8;28?l25k3:1(<o6:573?k7f03;07d:=b;29 
4g>2=?;7c?n8;08?l25i3:1(<o6:573?k7f03907d:=9;29 
4g>2=?;7c?n8;68?l2503:1(<o6:573?k7f03?07d:=6;29 
4g>2=?;7c?n8;48?l25=3:1(<o6:573?k7f03=07d:=4;29 
4g>2=?;7c?n8;:8?l25;3:1(<o6:573?k7f03307d:=2;29 
4g>2=?;7c?n8;c8?l2593:1(<o6:573?k7f03h07d:=0;29 
4g>2=?;7c?n8;a8?l26n3:1(<o6:573?k7f03n07d:>e;29 
4g>2=?;7c?n8;g8?l26l3:1(<o6:573?k7f03l07d:>b;29 
4g>2=?;7c?n8;33?>o39h0;6)?n9;664>h6i10:=65f40;94?"6i00?9=5a1`:957=<a=;36=4+1`;9006<f8k36<=4;h623?6=,8k269;?;o3b<?7332c?=;4?:%3b=?2282d:m54>5:9j043=83.:m44;519m5d>=9?10e9?;:18'5d?=<<:0b<o7:058?l26;3:1(<o6:573?k7f03;376g;1383>!7f13>><6`>a982=>=n<:91<7*>a88715=i9h21=l54i511>5<#9h3188>4n0c;>4d<3`>8=7>5$0c:>1373g;j47?l;:k775<72-;j57::0:l2e=<6l21b8?h50;&2e<<3=91e=l651d98m14b290/=l754428j4g?28l07d:=7;29
 
4g>2=?;7c?n8;03?>o39j0;6)?n9;664>h6i109=65f40394?"6i00?9=5a1`:967=<a=;;6=4+1`;9006<f8k36?=4;h636?6=3`>oj7>5$0c:>1c73g;j47>4;h6ga?6=,8k269k?;o3b<?7<3`>oh7>5$0c:>1c73g;j47<4;h6gg?6=,8k269k?;o3b<?5<3`>on7>5$0c:>1c73g;j47:4;h6ge?6=,8k269k?;o3b<?3<3`>o57>5$0c:>1c73g;j4784;h6g<?6=,8k269k?;o3b<?1<3`>o;7>5$0c:>1c73g;j4764;h6`e?6=,8k269mm;o3b<?6<3`>h57>5$0c:>1ee3g;j47?4;h6`<?6=,8k269mm;o3b<?4<3`>h;7>5$0c:>1ee3g;j47=4;h6`2?6=,8k269mm;o3b<?2<3`>h97>5$0c:>1ee3g;j47;4;h6`0?6=,8k269mm;o3b<?0<3`>h?7>5$0c:>1ee3g;j4794;h6`6?6=,8k269mm;o3b<?><3f>jh7>5;n63b?6=3`>nn7>5;c1e=?6=93:1<v*>b58e6>N4n11C?hk4og394?=zj:lj6=4>:183!7e<39nj6F<f99K7`c<g8k=6=44}c1g`?6=;3:1<v*>b58fe>N4n11C?hk4H2g8
 
42c2=lo7)hi:09j04<722c?o7>5;n3bf?6=3th8i;4?:283>5}#9k>1il5G3g:8L6cb3A9n7)?;d;6e`>"an3;0e9?50;9j0f<722e:mo4?::a7ae=8391<7>t$0`7>`g<@:l37E=je:J0a>"6<m0?ji5+fg82?l262900e9m50;9l5dd=831vn>k;:186>5<7s-;i87ki;I1e<>N4ml1C?h5+15f90cb<,ol1=6g;1;29?l242900e9m50;9j5dg=831d=ll50;9~f6c229086=4?{%3a0?cf3A9m46F<ed9K7`=#9=n18kj4$gd95>o393:17d:l:188k4ge2900qo=kb;291?6=8r.:n94jf:J0b==O;lo0D>k4$06g>1`c3-lm6<5f4083>>o3;3:17d:l:188m4gf2900c<om:188yg5b;3:187>50z&2f1<bm2B8j55G3dg8
 
c`=92c?=7>5;h6`>5<<a8kj6=44o0ca>5<<uk9n>7>54;294~"6j=0ni6F<f99K7`c<,ol1=6g;1;29?l2d2900e<on:188k4ge2900qo=jc;290?6=8r.:n94je:J0b==O;lo0(kh51:k75?6=3`>h6=44i0cb>5<<g8ki6=44}c1ff?6=<3:1<v*>b58fa>N4n11C?hk4$gd95>o393:17d:l:188m4gf2900c<om:188yg4em3:187>50z&2f1<bm2B8j55G3dg8
 
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\ No newline at end of file

Added: usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.sym
===================================================================
--- usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.sym                          
(rev 0)
+++ usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.sym  2008-07-15 23:44:44 UTC 
(rev 8894)
@@ -0,0 +1,60 @@
+VERSION 5
+BEGIN SYMBOL fifo_xlnx_512x36_2clk
+SYMBOLTYPE BLOCK
+TIMESTAMP 2008 7 14 23 25 11
+SYMPIN 0 80 Input din[35:0]
+SYMPIN 0 144 Input wr_en
+SYMPIN 0 176 Input wr_clk
+SYMPIN 0 240 Input rd_en
+SYMPIN 0 272 Input rd_clk
+SYMPIN 144 704 Input rst
+SYMPIN 576 80 Output dout[35:0]
+SYMPIN 576 208 Output full
+SYMPIN 576 432 Output empty
+BEGIN DISPLAY 32 32 TEXT fifo_xlnx_512x36_2clk
+    FONT 40 "Arial"
+END DISPLAY
+RECTANGLE N 32 32 544 672 
+BEGIN LINE W 0 80 32 80 
+END LINE
+BEGIN DISPLAY 36 80 PIN din[35:0] ATTR PinName
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 0 144 32 144 
+BEGIN DISPLAY 36 144 PIN wr_en ATTR PinName
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 0 176 32 176 
+BEGIN DISPLAY 36 176 PIN wr_clk ATTR PinName
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 0 240 32 240 
+BEGIN DISPLAY 36 240 PIN rd_en ATTR PinName
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 0 272 32 272 
+BEGIN DISPLAY 36 272 PIN rd_clk ATTR PinName
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 144 704 144 672 
+BEGIN DISPLAY 144 668 PIN rst ATTR PinName
+    ALIGNMENT BCENTER
+    FONT 24 "Arial"
+END DISPLAY
+BEGIN LINE W 576 80 544 80 
+END LINE
+BEGIN DISPLAY 540 80 PIN dout[35:0] ATTR PinName
+    ALIGNMENT RIGHT
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 576 208 544 208 
+BEGIN DISPLAY 540 208 PIN full ATTR PinName
+    ALIGNMENT RIGHT
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 576 432 544 432 
+BEGIN DISPLAY 540 432 PIN empty ATTR PinName
+    ALIGNMENT RIGHT
+    FONT 24 "Arial"
+END DISPLAY
+END SYMBOL

Added: usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.v
===================================================================
--- usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.v                            
(rev 0)
+++ usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.v    2008-07-15 23:44:44 UTC 
(rev 8894)
@@ -0,0 +1,169 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used             
*
+*     solely for design, simulation, implementation and creation of            
*
+*     design files limited to Xilinx devices or technologies. Use              
*
+*     with non-Xilinx devices or technologies is expressly prohibited          
*
+*     and immediately terminates your license.                                 
*
+*                                                                              
*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            
*
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  
*
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          
*
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              
*
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                
*
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  
*
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         
*
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 
*
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  
*
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           
*
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          
*
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          
*
+*     FOR A PARTICULAR PURPOSE.                                                
*
+*                                                                              
*
+*     Xilinx products are not intended for use in life support                 
*
+*     appliances, devices, or systems. Use in such applications are            
*
+*     expressly prohibited.                                                    
*
+*                                                                              
*
+*     (c) Copyright 1995-2007 Xilinx, Inc.                                     
*
+*     All rights reserved.                                                     
*
+*******************************************************************************/
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+// You must compile the wrapper file fifo_xlnx_512x36_2clk.v when simulating
+// the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+`timescale 1ns/1ps
+
+module fifo_xlnx_512x36_2clk(
+       din,
+       rd_clk,
+       rd_en,
+       rst,
+       wr_clk,
+       wr_en,
+       dout,
+       empty,
+       full);
+
+
+input [35 : 0] din;
+input rd_clk;
+input rd_en;
+input rst;
+input wr_clk;
+input wr_en;
+output [35 : 0] dout;
+output empty;
+output full;
+
+// synthesis translate_off
+
+      FIFO_GENERATOR_V4_3 #(
+               .C_COMMON_CLOCK(0),
+               .C_COUNT_TYPE(0),
+               .C_DATA_COUNT_WIDTH(9),
+               .C_DEFAULT_VALUE("BlankString"),
+               .C_DIN_WIDTH(36),
+               .C_DOUT_RST_VAL("0"),
+               .C_DOUT_WIDTH(36),
+               .C_ENABLE_RLOCS(0),
+               .C_FAMILY("spartan3"),
+               .C_FULL_FLAGS_RST_VAL(1),
+               .C_HAS_ALMOST_EMPTY(0),
+               .C_HAS_ALMOST_FULL(0),
+               .C_HAS_BACKUP(0),
+               .C_HAS_DATA_COUNT(0),
+               .C_HAS_INT_CLK(0),
+               .C_HAS_MEMINIT_FILE(0),
+               .C_HAS_OVERFLOW(0),
+               .C_HAS_RD_DATA_COUNT(0),
+               .C_HAS_RD_RST(0),
+               .C_HAS_RST(1),
+               .C_HAS_SRST(0),
+               .C_HAS_UNDERFLOW(0),
+               .C_HAS_VALID(0),
+               .C_HAS_WR_ACK(0),
+               .C_HAS_WR_DATA_COUNT(0),
+               .C_HAS_WR_RST(0),
+               .C_IMPLEMENTATION_TYPE(2),
+               .C_INIT_WR_PNTR_VAL(0),
+               .C_MEMORY_TYPE(1),
+               .C_MIF_FILE_NAME("BlankString"),
+               .C_MSGON_VAL(1),
+               .C_OPTIMIZATION_MODE(0),
+               .C_OVERFLOW_LOW(0),
+               .C_PRELOAD_LATENCY(0),
+               .C_PRELOAD_REGS(1),
+               .C_PRIM_FIFO_TYPE("512x36"),
+               .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
+               .C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
+               .C_PROG_EMPTY_TYPE(0),
+               .C_PROG_FULL_THRESH_ASSERT_VAL(511),
+               .C_PROG_FULL_THRESH_NEGATE_VAL(510),
+               .C_PROG_FULL_TYPE(0),
+               .C_RD_DATA_COUNT_WIDTH(9),
+               .C_RD_DEPTH(512),
+               .C_RD_FREQ(1),
+               .C_RD_PNTR_WIDTH(9),
+               .C_UNDERFLOW_LOW(0),
+               .C_USE_DOUT_RST(0),
+               .C_USE_ECC(0),
+               .C_USE_EMBEDDED_REG(0),
+               .C_USE_FIFO16_FLAGS(0),
+               .C_USE_FWFT_DATA_COUNT(0),
+               .C_VALID_LOW(0),
+               .C_WR_ACK_LOW(0),
+               .C_WR_DATA_COUNT_WIDTH(9),
+               .C_WR_DEPTH(512),
+               .C_WR_FREQ(1),
+               .C_WR_PNTR_WIDTH(9),
+               .C_WR_RESPONSE_LATENCY(1))
+       inst (
+               .DIN(din),
+               .RD_CLK(rd_clk),
+               .RD_EN(rd_en),
+               .RST(rst),
+               .WR_CLK(wr_clk),
+               .WR_EN(wr_en),
+               .DOUT(dout),
+               .EMPTY(empty),
+               .FULL(full),
+               .CLK(),
+               .INT_CLK(),
+               .BACKUP(),
+               .BACKUP_MARKER(),
+               .PROG_EMPTY_THRESH(),
+               .PROG_EMPTY_THRESH_ASSERT(),
+               .PROG_EMPTY_THRESH_NEGATE(),
+               .PROG_FULL_THRESH(),
+               .PROG_FULL_THRESH_ASSERT(),
+               .PROG_FULL_THRESH_NEGATE(),
+               .RD_RST(),
+               .SRST(),
+               .WR_RST(),
+               .ALMOST_EMPTY(),
+               .ALMOST_FULL(),
+               .DATA_COUNT(),
+               .OVERFLOW(),
+               .PROG_EMPTY(),
+               .PROG_FULL(),
+               .VALID(),
+               .RD_DATA_COUNT(),
+               .UNDERFLOW(),
+               .WR_ACK(),
+               .WR_DATA_COUNT(),
+               .SBITERR(),
+               .DBITERR());
+
+
+// synthesis translate_on
+
+// XST black box declaration
+// box_type "black_box"
+// synthesis attribute box_type of fifo_xlnx_512x36_2clk is "black_box"
+
+endmodule
+

Added: usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.veo
===================================================================
--- usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.veo                          
(rev 0)
+++ usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.veo  2008-07-15 23:44:44 UTC 
(rev 8894)
@@ -0,0 +1,51 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used             
*
+*     solely for design, simulation, implementation and creation of            
*
+*     design files limited to Xilinx devices or technologies. Use              
*
+*     with non-Xilinx devices or technologies is expressly prohibited          
*
+*     and immediately terminates your license.                                 
*
+*                                                                              
*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            
*
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  
*
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          
*
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              
*
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                
*
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  
*
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         
*
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 
*
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  
*
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           
*
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          
*
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          
*
+*     FOR A PARTICULAR PURPOSE.                                                
*
+*                                                                              
*
+*     Xilinx products are not intended for use in life support                 
*
+*     appliances, devices, or systems. Use in such applications are            
*
+*     expressly prohibited.                                                    
*
+*                                                                              
*
+*     (c) Copyright 1995-2007 Xilinx, Inc.                                     
*
+*     All rights reserved.                                                     
*
+*******************************************************************************/
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo_xlnx_512x36_2clk YourInstanceName (
+       .din(din), // Bus [35 : 0] 
+       .rd_clk(rd_clk),
+       .rd_en(rd_en),
+       .rst(rst),
+       .wr_clk(wr_clk),
+       .wr_en(wr_en),
+       .dout(dout), // Bus [35 : 0] 
+       .empty(empty),
+       .full(full));
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file fifo_xlnx_512x36_2clk.v when simulating
+// the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+

Added: usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.vhd
===================================================================
--- usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.vhd                          
(rev 0)
+++ usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.vhd  2008-07-15 23:44:44 UTC 
(rev 8894)
@@ -0,0 +1,150 @@
+--------------------------------------------------------------------------------
+--     This file is owned and controlled by Xilinx and must be used           
--
+--     solely for design, simulation, implementation and creation of          
--
+--     design files limited to Xilinx devices or technologies. Use            
--
+--     with non-Xilinx devices or technologies is expressly prohibited        
--
+--     and immediately terminates your license.                               
--
+--                                                                            
--
+--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          
--
+--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                
--
+--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        
--
+--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            
--
+--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              
--
+--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                
--
+--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       
--
+--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               
--
+--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                
--
+--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         
--
+--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        
--
+--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        
--
+--     FOR A PARTICULAR PURPOSE.                                              
--
+--                                                                            
--
+--     Xilinx products are not intended for use in life support               
--
+--     appliances, devices, or systems. Use in such applications are          
--
+--     expressly prohibited.                                                  
--
+--                                                                            
--
+--     (c) Copyright 1995-2007 Xilinx, Inc.                                   
--
+--     All rights reserved.                                                   
--
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file fifo_xlnx_512x36_2clk.vhd when simulating
+-- the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+Library XilinxCoreLib;
+-- synthesis translate_on
+ENTITY fifo_xlnx_512x36_2clk IS
+       port (
+       din: IN std_logic_VECTOR(35 downto 0);
+       rd_clk: IN std_logic;
+       rd_en: IN std_logic;
+       rst: IN std_logic;
+       wr_clk: IN std_logic;
+       wr_en: IN std_logic;
+       dout: OUT std_logic_VECTOR(35 downto 0);
+       empty: OUT std_logic;
+       full: OUT std_logic);
+END fifo_xlnx_512x36_2clk;
+
+ARCHITECTURE fifo_xlnx_512x36_2clk_a OF fifo_xlnx_512x36_2clk IS
+-- synthesis translate_off
+component wrapped_fifo_xlnx_512x36_2clk
+       port (
+       din: IN std_logic_VECTOR(35 downto 0);
+       rd_clk: IN std_logic;
+       rd_en: IN std_logic;
+       rst: IN std_logic;
+       wr_clk: IN std_logic;
+       wr_en: IN std_logic;
+       dout: OUT std_logic_VECTOR(35 downto 0);
+       empty: OUT std_logic;
+       full: OUT std_logic);
+end component;
+
+-- Configuration specification 
+       for all : wrapped_fifo_xlnx_512x36_2clk use entity 
XilinxCoreLib.fifo_generator_v4_3(behavioral)
+               generic map(
+                       c_has_int_clk => 0,
+                       c_rd_freq => 1,
+                       c_wr_response_latency => 1,
+                       c_has_srst => 0,
+                       c_has_rd_data_count => 0,
+                       c_din_width => 36,
+                       c_has_wr_data_count => 0,
+                       c_full_flags_rst_val => 1,
+                       c_implementation_type => 2,
+                       c_family => "spartan3",
+                       c_use_embedded_reg => 0,
+                       c_has_wr_rst => 0,
+                       c_wr_freq => 1,
+                       c_use_dout_rst => 0,
+                       c_underflow_low => 0,
+                       c_has_meminit_file => 0,
+                       c_has_overflow => 0,
+                       c_preload_latency => 0,
+                       c_dout_width => 36,
+                       c_msgon_val => 1,
+                       c_rd_depth => 512,
+                       c_default_value => "BlankString",
+                       c_mif_file_name => "BlankString",
+                       c_has_underflow => 0,
+                       c_has_rd_rst => 0,
+                       c_has_almost_full => 0,
+                       c_has_rst => 1,
+                       c_data_count_width => 9,
+                       c_has_wr_ack => 0,
+                       c_use_ecc => 0,
+                       c_wr_ack_low => 0,
+                       c_common_clock => 0,
+                       c_rd_pntr_width => 9,
+                       c_use_fwft_data_count => 0,
+                       c_has_almost_empty => 0,
+                       c_rd_data_count_width => 9,
+                       c_enable_rlocs => 0,
+                       c_wr_pntr_width => 9,
+                       c_overflow_low => 0,
+                       c_prog_empty_type => 0,
+                       c_optimization_mode => 0,
+                       c_wr_data_count_width => 9,
+                       c_preload_regs => 1,
+                       c_dout_rst_val => "0",
+                       c_has_data_count => 0,
+                       c_prog_full_thresh_negate_val => 510,
+                       c_wr_depth => 512,
+                       c_prog_empty_thresh_negate_val => 5,
+                       c_prog_empty_thresh_assert_val => 4,
+                       c_has_valid => 0,
+                       c_init_wr_pntr_val => 0,
+                       c_prog_full_thresh_assert_val => 511,
+                       c_use_fifo16_flags => 0,
+                       c_has_backup => 0,
+                       c_valid_low => 0,
+                       c_prim_fifo_type => "512x36",
+                       c_count_type => 0,
+                       c_prog_full_type => 0,
+                       c_memory_type => 1);
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_fifo_xlnx_512x36_2clk
+               port map (
+                       din => din,
+                       rd_clk => rd_clk,
+                       rd_en => rd_en,
+                       rst => rst,
+                       wr_clk => wr_clk,
+                       wr_en => wr_en,
+                       dout => dout,
+                       empty => empty,
+                       full => full);
+-- synthesis translate_on
+
+END fifo_xlnx_512x36_2clk_a;
+

Added: usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.vho
===================================================================
--- usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.vho                          
(rev 0)
+++ usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.vho  2008-07-15 23:44:44 UTC 
(rev 8894)
@@ -0,0 +1,72 @@
+--------------------------------------------------------------------------------
+--     This file is owned and controlled by Xilinx and must be used           
--
+--     solely for design, simulation, implementation and creation of          
--
+--     design files limited to Xilinx devices or technologies. Use            
--
+--     with non-Xilinx devices or technologies is expressly prohibited        
--
+--     and immediately terminates your license.                               
--
+--                                                                            
--
+--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          
--
+--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                
--
+--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        
--
+--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            
--
+--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              
--
+--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                
--
+--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       
--
+--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               
--
+--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                
--
+--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         
--
+--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        
--
+--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        
--
+--     FOR A PARTICULAR PURPOSE.                                              
--
+--                                                                            
--
+--     Xilinx products are not intended for use in life support               
--
+--     appliances, devices, or systems. Use in such applications are          
--
+--     expressly prohibited.                                                  
--
+--                                                                            
--
+--     (c) Copyright 1995-2007 Xilinx, Inc.                                   
--
+--     All rights reserved.                                                   
--
+--------------------------------------------------------------------------------
+-- The following code must appear in the VHDL architecture header:
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component fifo_xlnx_512x36_2clk
+       port (
+       din: IN std_logic_VECTOR(35 downto 0);
+       rd_clk: IN std_logic;
+       rd_en: IN std_logic;
+       rst: IN std_logic;
+       wr_clk: IN std_logic;
+       wr_en: IN std_logic;
+       dout: OUT std_logic_VECTOR(35 downto 0);
+       empty: OUT std_logic;
+       full: OUT std_logic);
+end component;
+
+-- Synplicity black box declaration
+attribute syn_black_box : boolean;
+attribute syn_black_box of fifo_xlnx_512x36_2clk: component is true;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : fifo_xlnx_512x36_2clk
+               port map (
+                       din => din,
+                       rd_clk => rd_clk,
+                       rd_en => rd_en,
+                       rst => rst,
+                       wr_clk => wr_clk,
+                       wr_en => wr_en,
+                       dout => dout,
+                       empty => empty,
+                       full => full);
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
+
+-- You must compile the wrapper file fifo_xlnx_512x36_2clk.vhd when simulating
+-- the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+

Added: usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.xco
===================================================================
--- usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.xco                          
(rev 0)
+++ usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk.xco  2008-07-15 23:44:44 UTC 
(rev 8894)
@@ -0,0 +1,82 @@
+##############################################################
+#
+# Xilinx Core Generator version K.37
+# Date: Mon Jul 14 23:25:42 2008
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = True
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc3s2000
+SET devicefamily = spartan3
+SET flowvendor = Foundation_iSE
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = False
+SET simulationfiles = Behavioral
+SET speedgrade = -5
+SET verilogsim = True
+SET vhdlsim = True
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 4.3
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET component_name=fifo_xlnx_512x36_2clk
+CSET data_count=false
+CSET data_count_width=9
+CSET disable_timing_violations=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=4
+CSET empty_threshold_negate_value=5
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET fifo_implementation=Independent_Clocks_Block_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=511
+CSET full_threshold_negate_value=510
+CSET input_data_width=36
+CSET input_depth=512
+CSET output_data_width=36
+CSET output_depth=512
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=First_Word_Fall_Through
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=No_Programmable_Full_Threshold
+CSET read_clock_frequency=1
+CSET read_data_count=false
+CSET read_data_count_width=9
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=false
+CSET use_embedded_registers=false
+CSET use_extra_logic=false
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=9
+# END Parameters
+GENERATE
+# CRC: 4753b01f
+

Added: 
usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso
===================================================================
--- 
usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso    
                            (rev 0)
+++ 
usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso    
    2008-07-15 23:44:44 UTC (rev 8894)
@@ -0,0 +1,3 @@
+blkmemdp_v6_2
+blk_mem_gen_v2_6
+fifo_generator_v4_3

Added: 
usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
===================================================================
--- 
usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
                               (rev 0)
+++ 
usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
       2008-07-15 23:44:44 UTC (rev 8894)
@@ -0,0 +1,101 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<document OS="lin64" product="ISE" version="10.1.02">
+
+  <!--The data in this file is primarily intended for consumption by Xilinx 
tools.
+    The structure and the elements are likely to change over the next few 
releases.
+    This means code written to parse this file will need to be revisited each 
subsequent release.-->
+
+  <application stringID="Xst" timeStamp="Mon Jul 14 16:25:16 2008">
+    <section stringID="XST_HDL_SYNTHESIS_REPORT">
+      <item dataType="int" stringID="XST_COUNTERS" value="2">
+        <item dataType="int" stringID="XST_9BIT_UP_COUNTER" value="2"/>
+      </item>
+      <item dataType="int" stringID="XST_REGISTERS" value="29">
+        <item dataType="int" stringID="XST_1BIT_REGISTER" value="15"/>
+        <item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/>
+        <item dataType="int" stringID="XST_3BIT_REGISTER" value="1"/>
+        <item dataType="int" stringID="XST_36BIT_REGISTER" value="1"/>
+        <item dataType="int" stringID="XST_9BIT_REGISTER" value="11"/>
+      </item>
+      <item dataType="int" stringID="XST_XORS" value="68">
+        <item dataType="int" stringID="XST_1BIT_XOR2" value="68"/>
+      </item>
+    </section>
+    <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
+      <item dataType="int" stringID="XST_FSMS" value="1"/>
+      <item dataType="int" stringID="XST_COUNTERS" value="2">
+        <item dataType="int" stringID="XST_9BIT_UP_COUNTER" value="2"/>
+      </item>
+      <item dataType="int" stringID="XST_REGISTERS" value="155">
+        <item dataType="int" stringID="XST_FLIPFLOPS" value="155"/>
+      </item>
+      <item dataType="int" stringID="XST_XORS" value="68">
+        <item dataType="int" stringID="XST_1BIT_XOR2" value="68"/>
+      </item>
+    </section>
+    <section stringID="XST_FINAL_REGISTER_REPORT">
+      <item dataType="int" stringID="XST_REGISTERS" value="170">
+        <item dataType="int" stringID="XST_FLIPFLOPS" value="170"/>
+      </item>
+    </section>
+    <section stringID="XST_PARTITION_REPORT">
+      <section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
+        <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
+      </section>
+    </section>
+    <section stringID="XST_FINAL_REPORT">
+      <section stringID="XST_FINAL_RESULTS">
+        <item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" 
value="tmp/_cg/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc"/>
+        <item stringID="XST_OUTPUT_FORMAT" value="NGC"/>
+        <item stringID="XST_OPTIMIZATION_GOAL" value="SPEED"/>
+        <item stringID="XST_KEEP_HIERARCHY" value="no"/>
+      </section>
+      <section stringID="XST_DESIGN_STATISTICS">
+        <item stringID="XST_IOS" value="177"/>
+      </section>
+      <section stringID="XST_CELL_USAGE">
+        <item dataType="int" stringID="XST_BELS" value="142">
+          <item dataType="int" stringID="XST_GND" value="1"/>
+          <item dataType="int" stringID="XST_LUT1" value="18"/>
+          <item dataType="int" stringID="XST_LUT2" value="28"/>
+          <item dataType="int" stringID="XST_LUT2L" value="2"/>
+          <item dataType="int" stringID="XST_LUT3" value="7"/>
+          <item dataType="int" stringID="XST_LUT3L" value="2"/>
+          <item dataType="int" stringID="XST_LUT4" value="29"/>
+          <item dataType="int" stringID="XST_MUXCY" value="36"/>
+          <item dataType="int" stringID="XST_VCC" value="1"/>
+          <item dataType="int" stringID="XST_XORCY" value="18"/>
+        </item>
+        <item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="170">
+          <item dataType="int" stringID="XST_FD" value="4"/>
+          <item dataType="int" stringID="XST_FDC" value="74"/>
+          <item dataType="int" stringID="XST_FDCE" value="42"/>
+          <item dataType="int" stringID="XST_FDE" value="36"/>
+          <item dataType="int" stringID="XST_FDP" value="9"/>
+          <item dataType="int" stringID="XST_FDPE" value="5"/>
+        </item>
+        <item dataType="int" stringID="XST_RAMS" value="1">
+          <item dataType="int" stringID="XST_RAMB16S36S36" value="1"/>
+        </item>
+      </section>
+    </section>
+    <section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
+      <item stringID="XST_SELECTED_DEVICE" value="3s2000fg456-5"/>
+      <item AVAILABLE="20480" dataType="int" stringID="XST_NUMBER_OF_SLICES" 
value="113"/>
+      <item AVAILABLE="40960" dataType="int" 
stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="170"/>
+      <item AVAILABLE="40960" dataType="int" 
stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="86"/>
+      <item dataType="int" stringID="XST_NUMBER_OF_IOS" value="177"/>
+      <item AVAILABLE="333" dataType="int" 
stringID="XST_NUMBER_OF_BONDED_IOBS" value="0"/>
+      <item AVAILABLE="40" dataType="int" stringID="XST_NUMBER_OF_BRAMS" 
value="1"/>
+    </section>
+    <section stringID="XST_PARTITION_RESOURCE_SUMMARY">
+      <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
+    </section>
+    <section stringID="XST_ERRORS_STATISTICS">
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" 
value="0"/>
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" 
value="131"/>
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" 
value="16"/>
+    </section>
+  </application>
+
+</document>

Added: usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk_flist.txt
===================================================================
--- usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk_flist.txt                    
        (rev 0)
+++ usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk_flist.txt    2008-07-15 
23:44:44 UTC (rev 8894)
@@ -0,0 +1,12 @@
+# Output products list for <fifo_xlnx_512x36_2clk>
+fifo_xlnx_512x36_2clk.asy
+fifo_xlnx_512x36_2clk.ngc
+fifo_xlnx_512x36_2clk.sym
+fifo_xlnx_512x36_2clk.v
+fifo_xlnx_512x36_2clk.veo
+fifo_xlnx_512x36_2clk.vhd
+fifo_xlnx_512x36_2clk.vho
+fifo_xlnx_512x36_2clk.xco
+fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
+fifo_xlnx_512x36_2clk_flist.txt
+fifo_xlnx_512x36_2clk_xmdf.tcl

Added: usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk_readme.txt
===================================================================
--- usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk_readme.txt                   
        (rev 0)
+++ usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk_readme.txt   2008-07-15 
23:44:44 UTC (rev 8894)
@@ -0,0 +1,55 @@
+The following files were generated for 'fifo_xlnx_512x36_2clk' in directory 
+/home/matt/usrp2/fpga/coregen:
+
+fifo_xlnx_512x36_2clk.asy:
+   Graphical symbol information file. Used by the ISE tools and some
+   third party tools to create a symbol representing the core.
+
+fifo_xlnx_512x36_2clk.ngc:
+   Binary Xilinx implementation netlist file containing the information
+   required to implement the module in a Xilinx (R) FPGA.
+
+fifo_xlnx_512x36_2clk.sym:
+   Please see the core data sheet.
+
+fifo_xlnx_512x36_2clk.v:
+   Verilog wrapper file provided to support functional simulation.
+   This file contains simulation model customization data that is
+   passed to a parameterized simulation model for the core.
+
+fifo_xlnx_512x36_2clk.veo:
+   VEO template file containing code that can be used as a model for
+   instantiating a CORE Generator module in a Verilog design.
+
+fifo_xlnx_512x36_2clk.vhd:
+   VHDL wrapper file provided to support functional simulation. This
+   file contains simulation model customization data that is passed to
+   a parameterized simulation model for the core.
+
+fifo_xlnx_512x36_2clk.vho:
+   VHO template file containing code that can be used as a model for
+   instantiating a CORE Generator module in a VHDL design.
+
+fifo_xlnx_512x36_2clk.xco:
+   CORE Generator input file containing the parameters used to
+   regenerate a core.
+
+fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt:
+   Please see the core data sheet.
+
+fifo_xlnx_512x36_2clk_flist.txt:
+   Text file listing all of the output files produced when a customized
+   core was generated in the CORE Generator.
+
+fifo_xlnx_512x36_2clk_readme.txt:
+   Text file indicating the files generated and how they are used.
+
+fifo_xlnx_512x36_2clk_xmdf.tcl:
+   ISE Project Navigator interface file. ISE uses this file to determine
+   how the files output by CORE Generator for the core can be integrated
+   into your ISE project.
+
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+

Added: usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl
===================================================================
--- usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl                     
        (rev 0)
+++ usrp2/trunk/fpga/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl     2008-07-15 
23:44:44 UTC (rev 8894)
@@ -0,0 +1,84 @@
+# The package naming convention is <core_name>_xmdf
+package provide fifo_xlnx_512x36_2clk_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::fifo_xlnx_512x36_2clk_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::fifo_xlnx_512x36_2clk_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name 
fifo_xlnx_512x36_2clk
+}
+# ::fifo_xlnx_512x36_2clk_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::fifo_xlnx_512x36_2clk_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path 
fifo_xlnx_512x36_2clk.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path 
fifo_xlnx_512x36_2clk.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path 
fifo_xlnx_512x36_2clk.sym
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path 
fifo_xlnx_512x36_2clk.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path 
fifo_xlnx_512x36_2clk.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path 
fifo_xlnx_512x36_2clk.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path 
fifo_xlnx_512x36_2clk.vho
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path 
fifo_xlnx_512x36_2clk.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path 
fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path 
fifo_xlnx_512x36_2clk_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module 
fifo_xlnx_512x36_2clk
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams

Modified: usrp2/trunk/fpga/eth/mac_txfifo_int.v
===================================================================
--- usrp2/trunk/fpga/eth/mac_txfifo_int.v       2008-07-15 22:51:59 UTC (rev 
8893)
+++ usrp2/trunk/fpga/eth/mac_txfifo_int.v       2008-07-15 23:44:44 UTC (rev 
8894)
@@ -1,6 +1,6 @@
 
 module mac_txfifo_int
-  (input clk, input rst,
+  (input clk, input rst, input mac_clk,
 
    // To MAC
    input Tx_mac_wa,
@@ -17,16 +17,20 @@
    output rd_error_o,
    input rd_sop_i,
    input rd_eop_i);
-   
-   
-   // Might as well use a shortfifo here since they are basically free
+
    wire  empty, full, sfifo_write, sfifo_read;
    wire [33:0] sfifo_in, sfifo_out;
-   
+
+   /*
    shortfifo #(.WIDTH(34)) txmac_sfifo
      (.clk(clk),.rst(rst),.clear(0),
       .datain(sfifo_in),.write(sfifo_write),.full(full),
       .dataout(sfifo_out),.read(sfifo_read),.empty(empty));
+    */
+   fifo_xlnx_512x36_2clk mac_tx_fifo_2clk
+     (.rst(rst),
+      .wr_clk(clk),.din({2'b0,sfifo_in}),.full(full),.wr_en(sfifo_write),
+      .rd_clk(mac_clk),.dout(sfifo_out),.empty(empty),.rd_en(sfifo_read));
    
    // MAC side signals
    //  We are allowed to do one more write after we are told the FIFO is full

Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v  2008-07-15 22:51:59 UTC (rev 
8893)
+++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v  2008-07-15 23:44:44 UTC (rev 
8894)
@@ -252,7 +252,8 @@
      U_MAC_tx(
     .Reset               ( Reset                ),
     .Clk                 ( MAC_tx_clk_div       ),
-    .Clk_user            ( Clk_user             ),
+    //.Clk_user            ( Clk_user             ),
+    .Clk_user            ( MAC_tx_clk_div             ),
 
     // PHY interface
     .TxD                 ( MTxD                 ),

Modified: usrp2/trunk/fpga/top/u2_core/u2_core.v
===================================================================
--- usrp2/trunk/fpga/top/u2_core/u2_core.v      2008-07-15 22:51:59 UTC (rev 
8893)
+++ usrp2/trunk/fpga/top/u2_core/u2_core.v      2008-07-15 23:44:44 UTC (rev 
8894)
@@ -145,8 +145,8 @@
    wire [31:0]         debug_gpio_0, debug_gpio_1;
    wire [31:0]         atr_lines;
 
-   wire [31:0]         debug_rx, debug_mac0, debug_mac1, debug_txc, 
debug_serdes0, debug_serdes1, debug_serdes2,
-               debug_rx_dsp;
+   wire [31:0]         debug_rx, debug_mac0, debug_mac1, debug_tx_dsp, 
debug_txc, 
+               debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp;
    // 
///////////////////////////////////////////////////////////////////////////////////////////////
    // Wishbone Single Master INTERCON
    parameter   dw = 32;  // Data bus width
@@ -432,7 +432,7 @@
       .wr_error_o(wr2_error),.wr_ready_i(wr2_ready),.wr_full_i(wr2_full) );
 
    mac_txfifo_int mac_txfifo_int
-     (.clk(dsp_clk),.rst(dsp_rst),
+     (.clk(dsp_clk),.rst(dsp_rst),.mac_clk(clk_to_mac),
       .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data),
       .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop),
       .rd_dat_i(rd2_dat),.rd_read_o(rd2_read),.rd_done_o(rd2_done),
@@ -540,7 +540,7 @@
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .dac_a(dac_a),.dac_b(dac_b),
-      .sample(sample_tx), .run(run_tx), .strobe(strobe_tx) );
+      .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), 
.debug(debug_tx_dsp) );
 
    assign dsp_rst = wb_rst;
 
@@ -621,10 +621,12 @@
    assign      debug_clk[0] = wb_clk;
    assign      debug_clk[1] = dsp_clk; 
    
-   //   assign      debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a},
+   //assign      debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a},
    //                  {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}};
 
-   assign      debug = 0; // debug_serdes0;
+   assign      debug = debug_tx_dsp;
+   
+   //assign      debug = 0; // debug_serdes0;
    assign      debug_gpio_0 = 0; // debug_serdes1;
    assign      debug_gpio_1 = 32'b0;