[Commit-gnuradio] r8907 - usrp2/trunk/fpga/sdr_lib

[matt]

Author: matt
Date: 2008-07-16 16:33:04 -0600 (Wed, 16 Jul 2008)
New Revision: 8907

Added:
   usrp2/trunk/fpga/sdr_lib/clip_and_round.v
   usrp2/trunk/fpga/sdr_lib/clip_and_round_reg.v
Modified:
   usrp2/trunk/fpga/sdr_lib/clip_reg.v
Log:
clip and round in one operation


Added: usrp2/trunk/fpga/sdr_lib/clip_and_round.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/clip_and_round.v                           (rev 0)
+++ usrp2/trunk/fpga/sdr_lib/clip_and_round.v   2008-07-16 22:33:04 UTC (rev 
8907)
@@ -0,0 +1,43 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2008 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+// Clipping "macro", keeps the bottom bits
+
+module clip_and_round
+  #(parameter bits_in=0,
+    parameter bits_out=0,
+    parameter clip_bits=0)
+    (input [bits_in-1:0] in,
+     output [bits_out-1:0] out);
+
+   wire [bits_out-1:0]            rounded;
+   
+   round #(.bits_in(bits_in-clip_bits),.bits_out(bits_out))
+     round (.in(in[bits_in-clip_bits-1:0]),.out(rounded));
+   
+   wire                   overflow = |in[bits_in-1:bits_in-clip_bits-1] 
+                          & ~(&in[bits_in-1:bits_in-clip_bits-1]);
+   
+   assign                 out = overflow ? 
+                          (in[bits_in-1] ? {1'b1,{(bits_out-1){1'b0}}} : 
{1'b0,{(bits_out-1){1'b1}}}) :
+                          rounded;
+   
+endmodule // clip_and_round

Added: usrp2/trunk/fpga/sdr_lib/clip_and_round_reg.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/clip_and_round_reg.v                               
(rev 0)
+++ usrp2/trunk/fpga/sdr_lib/clip_and_round_reg.v       2008-07-16 22:33:04 UTC 
(rev 8907)
@@ -0,0 +1,40 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2008 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+// Clipping "macro", keeps the bottom bits
+
+module clip_and_round_reg
+  #(parameter bits_in=0,
+    parameter bits_out=0,
+    parameter clip_bits=0)
+    (input clk,
+     input [bits_in-1:0] in,
+     output reg [bits_out-1:0] out);
+
+   wire [bits_out-1:0]            temp;
+
+   clip_and_round 
#(.bits_in(bits_in),.bits_out(bits_out),.clip_bits(clip_bits))
+     clip_and_round (.in(in),.out(temp));
+
+   always@(posedge clk)
+     out <= temp;
+   
+endmodule // clip_and_round_reg

Modified: usrp2/trunk/fpga/sdr_lib/clip_reg.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/clip_reg.v 2008-07-16 20:35:26 UTC (rev 8906)
+++ usrp2/trunk/fpga/sdr_lib/clip_reg.v 2008-07-16 22:33:04 UTC (rev 8907)
@@ -33,7 +33,6 @@
    clip #(.bits_in(bits_in),.bits_out(bits_out)) clip (.in(in),.out(temp));
    always @(posedge clk)
      out <= temp;
-
    
 endmodule // clip_reg