[Commit-gnuradio] r8918 - usrp2/trunk/fpga/sdr_lib

[matt]

Author: matt
Date: 2008-07-17 12:29:29 -0600 (Thu, 17 Jul 2008)
New Revision: 8918

Modified:
   usrp2/trunk/fpga/sdr_lib/hb_dec.v
Log:
fixes a timing problem and does all rounding in one step


Modified: usrp2/trunk/fpga/sdr_lib/hb_dec.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/hb_dec.v   2008-07-17 14:28:57 UTC (rev 8917)
+++ usrp2/trunk/fpga/sdr_lib/hb_dec.v   2008-07-17 18:29:29 UTC (rev 8918)
@@ -139,17 +139,18 @@
      acc (.clk(clk),.clear(clear),.acc(do_acc),.in(sum_of_prod),.out(acc_out));
 
    localparam          SHIFT_FACTOR = ACCWIDTH-IWIDTH-5;
-   wire [ACCWIDTH-1:0]         data_even_signext, final_sum_unrounded;
+   wire [ACCWIDTH-1:0]         data_even_signext;
+   wire [ACCWIDTH:0]   final_sum_unrounded;
 
    sign_extend #(.bits_in(IWIDTH),.bits_out(ACCWIDTH-SHIFT_FACTOR))
      signext_data_even 
(.in(data_even),.out(data_even_signext[ACCWIDTH-1:SHIFT_FACTOR]));
    assign              data_even_signext[SHIFT_FACTOR-1:0] = 0;
    
-   add2_and_round_reg #(.WIDTH(ACCWIDTH)) 
-     final_adder (.clk(clk), .in1(acc_out), .in2(data_even_signext), 
.sum(final_sum_unrounded));
+   add2_reg /* add2_and_round_reg */ #(.WIDTH(ACCWIDTH+1)) 
+     final_adder (.clk(clk), .in1({acc_out,1'b0}), 
.in2({data_even_signext,1'b0}), .sum(final_sum_unrounded));
 
-   round_reg #(.bits_in(ACCWIDTH-5),.bits_out(OWIDTH))
-     final_round 
(.clk(clk),.in(final_sum_unrounded[ACCWIDTH-6:0]),.out(final_sum));
+   round_reg #(.bits_in(ACCWIDTH-4),.bits_out(OWIDTH))
+     final_round 
(.clk(clk),.in(final_sum_unrounded[ACCWIDTH-5:0]),.out(final_sum));
 
    // Output
    always @(posedge clk)