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[Commit-gnuradio] r8921 - usrp2/trunk/fpga/eth/rtl/verilog
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From: |
matt |
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Subject: |
[Commit-gnuradio] r8921 - usrp2/trunk/fpga/eth/rtl/verilog |
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Date: |
Thu, 17 Jul 2008 12:35:09 -0600 (MDT) |
Author: matt
Date: 2008-07-17 12:35:07 -0600 (Thu, 17 Jul 2008)
New Revision: 8921
Modified:
usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v
usrp2/trunk/fpga/eth/rtl/verilog/Phy_int.v
Log:
Split out resets for the 3 different clock domains, but needs more work to
fully clean it up. The original author did not understand how to use async
resets properly. Also changed Phy_int.v to use verilog 2001 style.
Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v 2008-07-17 18:32:06 UTC (rev
8920)
+++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v 2008-07-17 18:35:07 UTC (rev
8921)
@@ -43,8 +43,10 @@
// System signals
input Clk_125M,
input Clk_user,
- output [2:0] Speed,
+ input rst_mac,
+ input rst_user,
+
// Wishbone compliant core host interface
input RST_I, // Active high (async) reset of the Wishbone interface
input CLK_I, // Wishbone interface clock (nominally 50 MHz)
@@ -94,6 +96,10 @@
output [31:0] debug1
);
+ wire rst_mac_rx = rst_mac;
+ wire rst_mac_tx = rst_mac;
+ wire [2:0] Speed;
+
wire [31:0] debug_rx;
wire [31:0] debug_tx0;
wire [31:0] debug_tx1;
@@ -102,9 +108,6 @@
// Local declarations
//-------------------------------------------------------------------------
- // Translate Wishbone specific naming to internal 'generic' names
- wire Reset = RST_I;
-
// RMON interface
wire [15:0] Rx_pkt_length_rmon;
wire Rx_apply_rmon;
@@ -201,7 +204,7 @@
MAC_rx #(.RX_FF_DEPTH(RX_FF_DEPTH))
U_MAC_rx(
- .Reset ( Reset ),
+ .Reset ( rst_mac_rx ),
.Clk_user ( Clk_user ),
.Clk ( MAC_rx_clk_div ),
@@ -250,7 +253,7 @@
MAC_tx #(.TX_FF_DEPTH(TX_FF_DEPTH))
U_MAC_tx(
- .Reset ( Reset ),
+ .Reset ( rst_mac_tx ),
.Clk ( MAC_tx_clk_div ),
//.Clk_user ( Clk_user ),
.Clk_user ( MAC_tx_clk_div ),
@@ -298,7 +301,7 @@
// Flow control outbound -- when other side sends PAUSE, we wait
flow_ctrl_tx flow_ctrl_tx
- (.rst(Reset),
+ (.rst(rst_mac_tx),
.tx_clk(MAC_tx_clk_div),
// Setting
.tx_pause_en ( tx_pause_en ),
@@ -311,7 +314,7 @@
);
flow_ctrl_rx flow_ctrl_rx // When we are running out of RX space, send a
PAUSE
- (.rst(Reset),
+ (.rst(rst_mac_rx), // FIXME
// Settings
.pause_frame_send_en ( pause_frame_send_en ),
.pause_quanta_set ( pause_quanta_set ),
@@ -330,7 +333,7 @@
RMON U_RMON(
.Clk ( CLK_I ),
- .Reset ( Reset ),
+ .Reset ( RST_I ),
// Tx RMON
.Tx_pkt_type_rmon ( Tx_pkt_type_rmon ),
@@ -351,21 +354,19 @@
.CPU_rd_dout ( CPU_rd_dout )
);
- Phy_int U_Phy_int(
- .Reset ( Reset ),
+ Phy_int U_Phy_int(
+ .rst_mac_rx ( rst_mac_rx ),
+ .rst_mac_tx ( rst_mac_tx ),
.MAC_rx_clk ( MAC_rx_clk ),
.MAC_tx_clk ( MAC_tx_clk ),
-
// Rx interface
.MCrs_dv ( MCrs_dv ),
.MRxD ( MRxD ),
.MRxErr ( MRxErr ),
-
// Tx interface
.MTxD ( MTxD ),
.MTxEn ( MTxEn ),
.MCRS ( MCRS ),
-
// PHY interface
.Tx_er ( Tx_er ),
.Tx_en ( Tx_en ),
@@ -375,14 +376,12 @@
.Rxd ( Rxd ),
.Crs ( Crs ),
.Col ( Col ),
-
// Host interface
.Line_loop_en( Line_loop_en ),
- .Speed ( Speed )
- );
+ .Speed ( Speed ) );
Clk_ctrl U_Clk_ctrl(
- .Reset ( Reset ),
+ .Reset ( rst_mac ),
.Clk_125M ( Clk_125M ),
// Host interface
@@ -402,7 +401,7 @@
eth_miim U_eth_miim(
.Clk ( CLK_I ),
- .Reset ( Reset ),
+ .Reset ( RST_I ),
.Divider ( Divider ),
.NoPre ( NoPre ),
.CtrlData ( CtrlData ),
Modified: usrp2/trunk/fpga/eth/rtl/verilog/Phy_int.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/Phy_int.v 2008-07-17 18:32:06 UTC (rev
8920)
+++ usrp2/trunk/fpga/eth/rtl/verilog/Phy_int.v 2008-07-17 18:35:07 UTC (rev
8921)
@@ -53,64 +53,36 @@
// no message
//
-module Phy_int (
- Reset,
- MAC_rx_clk,
- MAC_tx_clk,
+module Phy_int
+ (input rst_mac_rx,
+ input rst_mac_tx,
+ input MAC_rx_clk,
+ input MAC_tx_clk,
- // Rx interface
- MCrs_dv,
- MRxD,
- MRxErr,
+ // Rx interface
+ output reg MCrs_dv,
+ output reg [7:0] MRxD,
+ output MRxErr,
- // Tx interface
- MTxD,
- MTxEn,
- MCRS,
+ // Tx interface
+ input [7:0] MTxD,
+ input MTxEn,
+ output MCRS,
- // PHY interface
- Tx_er,
- Tx_en,
- Txd,
- Rx_er,
- Rx_dv,
- Rxd,
- Crs,
- Col,
+ // PHY interface
+ output Tx_er,
+ output reg Tx_en,
+ output reg [7:0] Txd,
+ input Rx_er,
+ input Rx_dv,
+ input [7:0] Rxd,
+ input Crs,
+ input Col,
- // Host interface
- Line_loop_en,
- Speed
-);
+ // Host interface
+ input Line_loop_en,
+ input [2:0] Speed );
- input Reset;
- input MAC_rx_clk;
- input MAC_tx_clk;
-
- // Rx interface
- output MCrs_dv;
- output [7:0] MRxD;
- output MRxErr;
-
- // Tx interface
- input [7:0] MTxD;
- input MTxEn;
- output MCRS;
-
- // PHY interface
- output Tx_er;
- output Tx_en;
- output [7:0] Txd;
- input Rx_er;
- input Rx_dv;
- input [7:0] Rxd;
- input Crs;
- input Col;
-
- // Host interface
- input Line_loop_en;
- input [2:0] Speed;
-
//-------------------------------------------------------------------------
// Local declarations
//-------------------------------------------------------------------------
@@ -119,10 +91,6 @@
reg MTxEn_dl1;
reg Tx_odd_data_ptr;
reg Rx_odd_data_ptr;
- reg Tx_en;
- reg [7:0] Txd;
- reg MCrs_dv;
- reg [7:0] MRxD;
reg Rx_er_dl1;
reg Rx_dv_dl1;
reg Rx_dv_dl2;
@@ -135,8 +103,8 @@
//-------------------------------------------------------------------------
// Reg boundary signals
- always @( posedge MAC_tx_clk or posedge Reset )
- if ( Reset )
+ always @( posedge MAC_tx_clk or posedge rst_mac_tx )
+ if ( rst_mac_tx )
begin
MTxD_dl1 <= 0;
MTxEn_dl1 <= 0;
@@ -147,8 +115,8 @@
MTxEn_dl1 <= MTxEn;
end
- always @( posedge MAC_tx_clk or posedge Reset )
- if ( Reset )
+ always @( posedge MAC_tx_clk or posedge rst_mac_tx )
+ if ( rst_mac_tx )
Tx_odd_data_ptr <= 0;
else if ( !MTxD_dl1 )
Tx_odd_data_ptr <= 0;
@@ -156,8 +124,8 @@
Tx_odd_data_ptr <= !Tx_odd_data_ptr;
- always @( posedge MAC_tx_clk or posedge Reset )
- if ( Reset )
+ always @( posedge MAC_tx_clk or posedge rst_mac_tx )
+ if ( rst_mac_tx )
Txd <= 0;
else if ( Speed[2] && MTxEn_dl1 )
Txd <= MTxD_dl1;
@@ -168,8 +136,8 @@
else
Txd <=0;
- always @( posedge MAC_tx_clk or posedge Reset )
- if ( Reset )
+ always @( posedge MAC_tx_clk or posedge rst_mac_tx )
+ if ( rst_mac_tx )
Tx_en <= 0;
else if ( MTxEn_dl1 )
Tx_en <= 1;
@@ -183,8 +151,8 @@
//-------------------------------------------------------------------------
// Reg boundery signals
- always @( posedge MAC_rx_clk or posedge Reset )
- if ( Reset )
+ always @( posedge MAC_rx_clk or posedge rst_mac_rx )
+ if ( rst_mac_rx )
begin
Rx_er_dl1 <= 0;
Rx_dv_dl1 <= 0;
@@ -206,8 +174,8 @@
assign MRxErr = Rx_er_dl1;
assign MCRS = Crs_dl1;
- always @( posedge MAC_rx_clk or posedge Reset )
- if ( Reset )
+ always @( posedge MAC_rx_clk or posedge rst_mac_rx )
+ if ( rst_mac_rx )
MCrs_dv <= 0;
else if ( Line_loop_en )
MCrs_dv <= Tx_en;
@@ -216,16 +184,16 @@
else
MCrs_dv <= 0;
- always @ ( posedge MAC_rx_clk or posedge Reset )
- if ( Reset )
+ always @ ( posedge MAC_rx_clk or posedge rst_mac_rx )
+ if ( rst_mac_rx )
Rx_odd_data_ptr <= 0;
else if ( !Rx_dv_dl1 )
Rx_odd_data_ptr <= 0;
else
Rx_odd_data_ptr <= !Rx_odd_data_ptr;
- always @ ( posedge MAC_rx_clk or posedge Reset )
- if ( Reset )
+ always @ ( posedge MAC_rx_clk or posedge rst_mac_rx )
+ if ( rst_mac_rx )
MRxD <= 0;
else if( Line_loop_en )
MRxD <= Txd;
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