[Commit-gnuradio] r8990 - in gnuradio/branches/developers/gnychis/fpga/usrp/fpga: inband_lib toplevel/usrp_inband_usb

[gnychis]

Author: gnychis
Date: 2008-07-23 18:08:08 -0600 (Wed, 23 Jul 2008)
New Revision: 8990

Modified:
   
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/rx_buffer_inband.v
   
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/tx_buffer_inband.v
   
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
Log:
making the timestamp clock inputs to the tx and rx buffers

Modified: 
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/rx_buffer_inband.v
===================================================================
--- 
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/rx_buffer_inband.v
   2008-07-24 00:03:16 UTC (rev 8989)
+++ 
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/rx_buffer_inband.v
   2008-07-24 00:08:08 UTC (rev 8990)
@@ -1,7 +1,8 @@
 //`include "../../firmware/include/fpga_regs_common.v"
 //`include "../../firmware/include/fpga_regs_standard.v"
 module rx_buffer_inband
-  ( input usbclk,
+  ( input timestamp_clock,
+    input usbclk,
     input bus_reset,
     input reset,  // DSP side reset (used here), do not reset registers
     input reset_regs, //Only reset registers
@@ -50,14 +51,6 @@
             read_count <= #1 read_count + 9'd1;
         else
             read_count <= #1 RD ? read_count : 9'b0;
-       
-       // Time counter
-       reg [31:0] timestamp_clock;
-       always @(posedge rxclk)
-               if (clock_reset)
-                       timestamp_clock <= 0;
-               else
-                       timestamp_clock <= timestamp_clock + 1;
      
   // USB side fifo
   wire [11:0] rdusedw;

Modified: 
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/tx_buffer_inband.v
===================================================================
--- 
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/tx_buffer_inband.v
   2008-07-24 00:03:16 UTC (rev 8989)
+++ 
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/tx_buffer_inband.v
   2008-07-24 00:08:08 UTC (rev 8990)
@@ -1,6 +1,6 @@
 module tx_buffer_inband
   ( //System
-    input wire usbclk, input wire bus_reset, input wire reset, input wire 
clock_reset,
+    input wire timestamp_clock, input wire usbclk, input wire bus_reset, input 
wire reset, input wire clock_reset,
     input wire [15:0] usbdata, output wire have_space, input wire [3:0] 
channels, 
     //output transmit signals
     output wire [15:0] tx_i_0, output wire [15:0] tx_q_0, 
@@ -28,7 +28,6 @@
    genvar i ;
     
    /* These will eventually be external register */
-   reg                  [31:0] timestamp_clock ;
    wire                 [7:0]  txstrobe_rate [NUM_CHAN-1:0] ;
    wire                                [31:0] rssi [3:0];
    assign rssi[0] = rssi_0;
@@ -36,13 +35,6 @@
    assign rssi[2] = rssi_2;
    assign rssi[3] = rssi_3;
    
-   always @(posedge txclk)
-       if (clock_reset)
-           timestamp_clock <= 0;
-       else
-           timestamp_clock <= timestamp_clock + 1;
-
-
     /* Connections between tx_usb_fifo_reader and
        cnannel/command processing blocks */
    wire                  [31:0] tx_data_bus ;

Modified: 
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
===================================================================
--- 
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
      2008-07-24 00:03:16 UTC (rev 8989)
+++ 
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
      2008-07-24 00:08:08 UTC (rev 8990)
@@ -139,7 +139,7 @@
 
 `ifdef TX_IN_BAND
        tx_buffer_inband tx_buffer
-     ( 
.usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),.clock_reset(tx_dsp_reset),
+     ( 
.timestamp_clock(timestamp_clock),.usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),.clock_reset(tx_dsp_reset),
        .usbdata(usbdata),.WR(WR),.have_space(have_space),
        .tx_underrun(tx_underrun),.channels({tx_numchan,1'b0}),
        .tx_i_0(ch0tx),.tx_q_0(ch1tx),
@@ -265,7 +265,7 @@
                               
.ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan));
    `ifdef RX_IN_BAND
    rx_buffer_inband rx_buffer
-     ( 
.usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),.clock_reset(tx_dsp_reset),
+     ( 
.timestamp_clock(timestamp_clock),.usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),.clock_reset(tx_dsp_reset),
        .reset_regs(rx_dsp_reset),
        
.usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
        .channels(rx_numchan),