[Commit-gnuradio] r9018 - in gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib: . testbenches

[gnychis]

Author: gnychis
Date: 2008-07-25 16:07:36 -0600 (Fri, 25 Jul 2008)
New Revision: 9018

Modified:
   
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/rx_buffer_inband.v
   
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/tb_timestamps.v
   
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/tx_buffer_inband.v
Log:
fixing input and working on testbench

Modified: 
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/rx_buffer_inband.v
===================================================================
--- 
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/rx_buffer_inband.v
   2008-07-25 21:48:00 UTC (rev 9017)
+++ 
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/rx_buffer_inband.v
   2008-07-25 22:07:36 UTC (rev 9018)
@@ -1,7 +1,7 @@
 //`include "../../firmware/include/fpga_regs_common.v"
 //`include "../../firmware/include/fpga_regs_standard.v"
 module rx_buffer_inband
-  ( input timestamp_clock,
+  ( input wire [31:0] timestamp_clock,
     input usbclk,
     input bus_reset,
     input reset,  // DSP side reset (used here), do not reset registers

Modified: 
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/tb_timestamps.v
===================================================================
--- 
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/tb_timestamps.v
  2008-07-25 21:48:00 UTC (rev 9017)
+++ 
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/tb_timestamps.v
  2008-07-25 22:07:36 UTC (rev 9018)
@@ -42,4 +42,21 @@
   always
     #5 rxclk = ~rxclk;
 
+  initial
+    begin
+      bus_reset = 1;
+      clock_reset = 1;
+      reset_regs = 1;
+      reset   = 1;
+      rxclk   = 0;
+      ch_0    = 0;
+      ch_1    = 0;
+    end
+
+    begin
+    @(posedge rxstrobe)
+      ch_0 = 16'd0;
+      ch_1 = 16'd1;
+    end  
+  end
 endmodule

Modified: 
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/tx_buffer_inband.v
===================================================================
--- 
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/tx_buffer_inband.v
   2008-07-25 21:48:00 UTC (rev 9017)
+++ 
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/tx_buffer_inband.v
   2008-07-25 22:07:36 UTC (rev 9018)
@@ -1,6 +1,6 @@
 module tx_buffer_inband
   ( //System
-    input wire timestamp_clock, input wire usbclk, input wire bus_reset, input 
wire reset, input wire clock_reset,
+    input wire [31:0] timestamp_clock, input wire usbclk, input wire 
bus_reset, input wire reset, input wire clock_reset,
     input wire [15:0] usbdata, output wire have_space, input wire [3:0] 
channels, 
     //output transmit signals
     output wire [15:0] tx_i_0, output wire [15:0] tx_q_0,