[Commit-gnuradio] r9104 - usrp2/trunk/fpga/serdes

[matt]

Author: matt
Date: 2008-07-31 20:35:03 -0600 (Thu, 31 Jul 2008)
New Revision: 9104

Modified:
   usrp2/trunk/fpga/serdes/serdes_rx.v
Log:
pass fifo information out, do retiming of xon/xoff in here, retime rst to get 
it into the proper clock domain


Modified: usrp2/trunk/fpga/serdes/serdes_rx.v
===================================================================
--- usrp2/trunk/fpga/serdes/serdes_rx.v 2008-08-01 02:33:30 UTC (rev 9103)
+++ usrp2/trunk/fpga/serdes/serdes_rx.v 2008-08-01 02:35:03 UTC (rev 9104)
@@ -40,6 +40,8 @@
 
      output [15:0] fifo_space,
      output xon_rcvd, output xoff_rcvd,
+
+     output [15:0] fifo_occupied, output fifo_full, output fifo_empty,
      output [31:0] debug
      );
 
@@ -80,6 +82,8 @@
    wire [15:0] nextCRC;
    reg                write_d;
 
+   oneshot_2clk 
rst_1s(.clk_in(clk),.in(rst),.clk_out(ser_rx_clk),.out(rst_rxclk));
+
    /*
    ss_rcvr #(.WIDTH(18)) ss_rcvr
      (.rxclk(ser_rx_clk),.sysclk(clk),.rst(rst),
@@ -89,34 +93,42 @@
    assign      even_data = {ser_rkmsb,ser_rklsb,ser_r};
    
    always @(posedge ser_rx_clk)
-     if(rst)
+     if(rst_rxclk)
        holder <= 9'd0;
      else
        holder <= {even_data[17],even_data[15:8]};
    
    always @(posedge ser_rx_clk)
-     if(rst)
+     if(rst_rxclk)
        odd_data <= 18'd0;
      else
        odd_data <= {even_data[16],holder[8],even_data[7:0],holder[7:0]};
    
    assign      chosen_data = odd ? odd_data : even_data;
 
-   assign      xon_rcvd = ({1'b1,K_XON} == {ser_rkmsb,ser_r[15:8]}) | 
({1'b1,K_XON} == {ser_rklsb,ser_r[7:0]} );
-   assign      xoff_rcvd = ({1'b1,K_XOFF} == {ser_rkmsb,ser_r[15:8]}) | 
({1'b1,K_XOFF} == {ser_rklsb,ser_r[7:0]} );
+   // Transfer xon and xoff info to the main system clock for flow control 
purposes
+   reg                xon_rcvd_rxclk, xoff_rcvd_rxclk;
+   always @(posedge ser_rx_clk)
+     xon_rcvd_rxclk = ({1'b1,K_XON} == {ser_rkmsb,ser_r[15:8]}) | 
({1'b1,K_XON} == {ser_rklsb,ser_r[7:0]} );
+   always @(posedge ser_rx_clk)
+     xoff_rcvd_rxclk = ({1'b1,K_XOFF} == {ser_rkmsb,ser_r[15:8]}) | 
({1'b1,K_XOFF} == {ser_rklsb,ser_r[7:0]} );
+   
+   oneshot_2clk 
xon_1s(.clk_in(ser_rx_clk),.in(xon_rcvd_rxclk),.clk_out(clk),.out(xon_rcvd));
+   oneshot_2clk 
xoff_1s(.clk_in(ser_rx_clk),.in(xoff_rcvd_rxclk),.clk_out(clk),.out(xoff_rcvd));
 
+   // If the other side is sending xon or xoff, or is flow controlled (b/c we 
told them to be), don't fill the fifos
    wire        wait_here = ((chosen_data == {2'b10,K_COMMA,D_56})||
                            (chosen_data == {2'b11,K_XON,K_XON})||
                            (chosen_data == {2'b11,K_XOFF,K_XOFF}) );
 
    always @(posedge ser_rx_clk)
-     if(rst) sop_i <= 0;
+     if(rst_rxclk) sop_i <= 0;
      else if(state == FIRSTLINE1) sop_i <= 1;
      else if(write_d) sop_i <= 0;
    
    reg                write_pre;
    always @(posedge ser_rx_clk)
-     if(rst)
+     if(rst_rxclk)
        begin
          state <= IDLE;
          odd <= 0;
@@ -237,7 +249,7 @@
    
    
    always @(posedge ser_rx_clk)
-     if(rst)
+     if(rst_rxclk)
        CRC <= 16'hFFFF;
      else if(state == IDLE)
        CRC <= 16'hFFFF;
@@ -247,7 +259,7 @@
    CRC16_D16 crc_blk(chosen_data[15:0],CRC,nextCRC);
 
    always @(posedge ser_rx_clk)
-     if(rst) write_d <= 0;
+     if(rst_rxclk) write_d <= 0;
      else write_d <= write_pre;
 
    // Internal FIFO, size 9 is 2K, size 10 is 4K Bytes
@@ -256,14 +268,16 @@
 
 //`define CASC 1
 `define MYFIFO 1   
-//`define XILFIFO1
+//`define XILFIFO 1
 
 `ifdef CASC   
    cascadefifo2 #(.WIDTH(35),.SIZE(FIFOSIZE)) serdes_rx_fifo
      (.clk(clk),.rst(rst),.clear(0),
       .datain({error_i,sop_i,eop_i,line_i}), .write(write), .full(full),
       .dataout({error_o,sop_o,eop_o,line_o}), .read(read), .empty(empty),
-      .fifo_space(fifo_space) );
+      .space(fifo_space),.occupied(fifo_occupied) );
+   assign fifo_full = full;
+   assign fifo_empty = empty;
 `endif
 
 `ifdef MYFIFO
@@ -275,6 +289,9 @@
       .level_rclk(level) );
    assign             fifo_space = {{(16-FIFOSIZE){1'b0}},{FIFOSIZE{1'b1}}} - 
                       {{(16-FIFOSIZE){1'b0}},level};
+   assign             fifo_occupied = { {(16-FIFOSIZE){1'b0}} ,level};
+   assign             fifo_full = full;   // Note -- fifo_full is in the wrong 
clock domain
+   assign             fifo_empty = empty;
 `endif
 
 `ifdef XILFIFO
@@ -289,10 +306,13 @@
       .dout({error_o,sop_o,eop_o,line_o}),
       .empty(empty),
       .full(full),
-      .rd_data_count(),
-      .wr_data_count(level));
+      .rd_data_count(level),
+      .wr_data_count() );
    assign             fifo_space = {{(16-FIFOSIZE){1'b0}},{FIFOSIZE{1'b1}}} - 
                       {{(16-FIFOSIZE){1'b0}},level};
+   assign             fifo_occupied = { {(16-FIFOSIZE){1'b0}}, level };
+   assign             fifo_full = full;   // Note -- fifo_full is in the wrong 
clock domain
+   assign             fifo_empty = empty;
 `endif //  `ifdef XILFIFO
    
    
@@ -321,9 +341,7 @@
                    { fifo_space[7:0] },
                    { 2'd0, error_i, sop_i, eop_i, error_o, sop_o, eop_o },
                    { full, empty, write, read, xfer_active, state[2:0] } };
-   */
 
-   /*
    assign      debug = { { xoff_rcvd,xon_rcvd,sop_i,eop_i,error_i,state[2:0] },
                         { odd, wait_here, write_pre, write_d, write, full, 
chosen_data[17:16]},
                         { chosen_data[15:8] },