[Commit-gnuradio] r9301 - usrp2/trunk/fpga/control_lib

[matt]

Author: matt
Date: 2008-08-16 22:48:42 -0600 (Sat, 16 Aug 2008)
New Revision: 9301

Added:
   usrp2/trunk/fpga/control_lib/sd_spi.v
   usrp2/trunk/fpga/control_lib/sd_spi_tb.v
   usrp2/trunk/fpga/control_lib/sd_spi_wb.v
Log:
SD card spi communications module


Added: usrp2/trunk/fpga/control_lib/sd_spi.v
===================================================================
--- usrp2/trunk/fpga/control_lib/sd_spi.v                               (rev 0)
+++ usrp2/trunk/fpga/control_lib/sd_spi.v       2008-08-17 04:48:42 UTC (rev 
9301)
@@ -0,0 +1,70 @@
+module sd_spi
+  (input clk,
+   input rst,
+   
+   // SD Card interface
+   output reg sd_clk,
+   output sd_mosi,
+   input sd_miso,
+   
+   // Controls
+   input [7:0] clk_div,
+   input [7:0] send_dat,
+   output [7:0] rcv_dat,
+   input go,
+   output ready);
+
+   reg [7:0] clk_ctr;   
+   reg [3:0] bit_ctr;
+
+   wire      bit_ready = (clk_ctr == 8'd0);
+   wire      bit_busy = (clk_ctr != 8'd0);
+   wire      bit_done = (clk_ctr == clk_div);
+
+   wire      send_clk_hi = (clk_ctr == (clk_div>>1));
+   wire      latch_dat = (clk_ctr == (clk_div - 8'd2));     
+   wire      send_clk_lo = (clk_ctr == (clk_div - 8'd1));
+
+   wire      send_bit = (bit_ready && (bit_ctr != 0));
+   assign    ready = (bit_ctr == 0);
+   
+   always @(posedge clk)
+     if(rst)
+       clk_ctr <= 0;
+     else if(bit_done)
+       clk_ctr <= 0;
+     else if(bit_busy)
+       clk_ctr <= clk_ctr + 1;
+     else if(send_bit)
+       clk_ctr <= 1;
+
+   always @(posedge clk)
+     if(rst)
+       sd_clk <= 0;
+     else if(send_clk_hi)
+       sd_clk <= 1;
+     else if(send_clk_lo)
+       sd_clk <= 0;
+   
+   always @(posedge clk)
+     if(rst)
+       bit_ctr <= 0;
+     else if(bit_done)
+       if(bit_ctr == 4'd8)
+        bit_ctr <= 0;
+       else
+        bit_ctr <= bit_ctr + 1;
+     else if(bit_ready & go)
+       bit_ctr <= 1;
+   
+   reg [7:0] shift_reg;
+   always @(posedge clk)
+     if(go)
+       shift_reg <= send_dat;
+     else if(latch_dat)
+       shift_reg <= {shift_reg[6:0],sd_miso};
+
+   assign    sd_mosi = shift_reg[7];
+   assign    rcv_dat = shift_reg;
+   
+endmodule // sd_spi

Added: usrp2/trunk/fpga/control_lib/sd_spi_tb.v
===================================================================
--- usrp2/trunk/fpga/control_lib/sd_spi_tb.v                            (rev 0)
+++ usrp2/trunk/fpga/control_lib/sd_spi_tb.v    2008-08-17 04:48:42 UTC (rev 
9301)
@@ -0,0 +1,40 @@
+
+
+module sd_spi_tb;
+
+   reg clk = 0;
+   always #5 clk = ~clk;
+   reg rst = 1;
+   initial #32 rst = 0;
+
+   wire sd_clk, sd_mosi, sd_miso;
+   wire [7:0] clk_div = 12;
+   wire [7:0] send_dat = 23;
+   wire [7:0] rcv_dat;
+
+   wire       ready;
+   reg               go = 0;
+   initial 
+     begin
+       repeat (100)
+         @(posedge clk);
+       go <= 1;
+       @(posedge clk);
+       go <= 0;
+     end
+   
+   sd_spi dut(.clk(clk),.rst(rst),
+             .sd_clk(sd_clk),.sd_mosi(sd_mosi),.sd_miso(sd_miso),
+             .clk_div(clk_div),.send_dat(send_dat),.rcv_dat(rcv_dat),
+             .go(go),.ready(ready) );
+
+   initial    
+     begin 
+       $dumpfile("sd_spi_tb.vcd");
+       $dumpvars(0,sd_spi_tb);
+     end
+
+   initial
+     #10000 $finish();
+   
+endmodule // sd_spi_tb

Added: usrp2/trunk/fpga/control_lib/sd_spi_wb.v
===================================================================
--- usrp2/trunk/fpga/control_lib/sd_spi_wb.v                            (rev 0)
+++ usrp2/trunk/fpga/control_lib/sd_spi_wb.v    2008-08-17 04:48:42 UTC (rev 
9301)
@@ -0,0 +1,66 @@
+
+// Wishbone module for spi communications with an SD Card
+// The programming interface is simple -- 
+//      Write the desired clock divider to address 1 (should be 1 or higher)
+//      Status is in address 0.  A 1 indicates the last transaction is done 
and it is safe to
+//          send another
+//      Writing a byte to address 2 sends that byte over SPI.  When it is 
done, 
+//          status (addr 0) goes high again, and the received byte can be read 
from address 3.
+
+module sd_spi_wb
+  (input clk,
+   input rst,
+   
+   // SD Card interface
+   output sd_clk,
+   output sd_csn,
+   output sd_mosi,
+   input sd_miso,
+
+   input wb_cyc_i,
+   input wb_stb_i,
+   input wb_we_i,
+   input [1:0] wb_adr_i,
+   input [7:0] wb_dat_i,
+   output reg [7:0] wb_dat_o,
+   output reg wb_ack_o);
+
+   localparam ADDR_STATUS = 0;
+   localparam ADDR_CLKDIV = 1;
+   localparam ADDR_WRITE = 2;
+   localparam ADDR_READ = 3;
+
+   wire [7:0] status, rcv_dat;
+   reg [7:0]  clkdiv;
+   wire       ready;
+   reg               ack_d1;
+   always @(posedge clk)
+     if(rst) ack_d1 <= 0;
+     else ack_d1 <= wb_ack_o;
+   
+   always @(posedge clk)
+     if(rst) wb_ack_o <= 0;
+     else wb_ack_o <= wb_cyc_i & wb_stb_i & ~ack_d1;
+   
+   always @(posedge clk)
+     case(wb_adr_i)
+       ADDR_STATUS : wb_dat_o <= {7'd0,ready};
+       ADDR_CLKDIV : wb_dat_o <= clkdiv;
+       ADDR_READ : wb_dat_o <= rcv_dat;
+       default : wb_dat_o <= 0;
+     endcase // case(wb_adr_i)
+
+   always @(posedge clk)
+     if(wb_we_i & wb_stb_i & wb_cyc_i & wb_ack_o)
+       case(wb_adr_i)
+        ADDR_CLKDIV : clkdiv <= wb_dat_i;
+       endcase // case(wb_adr_i)
+
+   wire       go = wb_we_i & wb_stb_i & wb_cyc_i & wb_ack_o & (wb_adr_i == 
ADDR_WRITE);
+   
+   sd_spi sd_spi(.clk(clk),.rst(rst),
+                .sd_clk(sd_clk),.sd_mosi(sd_mosi),.sd_miso(sd_miso),
+                .clk_div(clkdiv),.send_dat(wb_dat_i),.rcv_dat(rcv_dat),
+                .go(go),.ready(ready) );
+
+endmodule // sd_spi_wb