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[Commit-gnuradio] r9516 - in gnuradio/branches/developers/ets/inband/usr
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From: |
ets |
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Subject: |
[Commit-gnuradio] r9516 - in gnuradio/branches/developers/ets/inband/usrp/fpga: inband_lib inband_lib/tb megacells toplevel/usrp_inband_usb |
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Date: |
Sun, 7 Sep 2008 02:20:22 -0600 (MDT) |
Author: ets
Date: 2008-09-07 02:20:22 -0600 (Sun, 07 Sep 2008)
New Revision: 9516
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/inband_packet_defs.v
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_channel_buffer.v
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.qpf
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.qsf
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.v
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.vwf
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.bsf
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.cmp
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.inc
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.qip
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.v
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la_bb.v
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la_inst.v
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.bsf
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.cmp
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.inc
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.qip
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.v
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la_bb.v
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la_inst.v
Modified:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/packet_builder.v
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
gnuradio/branches/developers/ets/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
Log:
new rx_buffer_inband
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/inband_packet_defs.v
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/inband_packet_defs.v
(rev 0)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/inband_packet_defs.v
2008-09-07 08:20:22 UTC (rev 9516)
@@ -0,0 +1,55 @@
+ //Inband packet defines
+
+`define MAXPAYLOAD 504
+`define PAD_VALUE 16'hDEAD
+
+ //Packet line locations (16b wide)
+`define RD_HEADER1 8'd0
+`define RD_HEADER2 8'd1
+`define RD_TIMESTAMP1 8'd2
+`define RD_TIMESTAMP2 8'd3
+`define RD_LAST 8'd255
+
+ // Final header component allignments
+ // in 16b wide lines
+ // Header1 bits
+`define PAYLOAD_LEN 8:0
+`define TAG 12:9
+`define MBZ 15:13
+
+ // Header2 bits
+`define CHAN 4:0
+`define RSSI 10:5
+`define BURST_END 11
+`define BURST_START 12
+`define DROPPED 13
+`define UNDERRUN 14
+`define OVERRUN 15
+
+
+// Channel buffer header fifo bits (64b wide)
+// These arranged to simplify the masking logic
+// of modifying certain fields
+
+//generated by channel_buffer
+`define CB_PAYLOAD_LEN 8:0 //9
+`define CB_OVERRUN 9 //1
+
+//inputs
+`define CB_CHAN 14:10 //5
+`define CB_RSSI 20:15 //6
+`define CB_TIMESTAMP 52:21 //32
+`define CB_UNDERRUN 53 //1
+
+//currently unused
+`define CB_DROPPED 54 //1
+`define CB_TAG 58:55 //4
+`define CB_BURST_END 59 //1
+`define CB_BURST_START 60 //1
+`define CB_MBZ 63:61 //3
+
+`define CB_NON_INPUTS 63:54 //unset header values
+`define CB_NI_SIZE 28
+
+`define CB_PASSTHROUGH 63:10 //Everything non-generated
+`define CB_PT_SIZE 54
Modified:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/packet_builder.v
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/packet_builder.v
2008-09-07 06:36:29 UTC (rev 9515)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/packet_builder.v
2008-09-07 08:20:22 UTC (rev 9516)
@@ -1,152 +1,139 @@
-module packet_builder #(parameter NUM_CHAN = 2)(
- // System
- input rxclk,
- input reset,
- input [31:0] timestamp_clock,
- input [3:0] channels,
- // ADC side
- input [15:0]chan_fifodata,
- input [NUM_CHAN:0]chan_empty,
- input [9:0]chan_usedw,
- output reg [3:0]rd_select,
- output reg chan_rdreq,
- // FX2 side
- output reg WR,
- output reg [15:0]fifodata,
- input have_space,
- input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire [31:0]rssi_2,
- input wire [31:0]rssi_3, output wire [7:0] debugbus,
- input [NUM_CHAN:0] underrun);
-
-
- // States
- `define IDLE 3'd0
- `define HEADER1 3'd1
- `define HEADER2 3'd2
- `define TIMESTAMP 3'd3
- `define FORWARD 3'd4
-
- `define MAXPAYLOAD 504
-
- `define PAYLOAD_LEN 8:0
- `define TAG 12:9
- `define MBZ 15:13
-
- `define CHAN 4:0
- `define RSSI 10:5
- `define BURST 12:11
- `define DROPPED 13
- `define UNDERRUN 14
- `define OVERRUN 15
-
- reg [NUM_CHAN:0] overrun;
- reg [2:0] state;
- reg [8:0] read_length;
- reg [8:0] payload_len;
- reg timestamp_complete;
- reg [3:0] check_next;
-
- wire [31:0] true_rssi;
- wire [4:0] true_channel;
- wire ready_to_send;
-
- assign debugbus = {chan_empty[0], rd_select[0], have_space,
- (chan_usedw >= 10'd504), (chan_usedw ==0),
- ready_to_send, state[1:0]};
-
- assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) :
- ((rd_select[0]) ?
rssi_1:rssi_0);
- assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next -
4'd1});
- assign ready_to_send = (chan_usedw >= 10'd504) || (chan_usedw == 0) ||
- ((rd_select == NUM_CHAN)&&(chan_usedw > 0));
-
- always @(posedge rxclk)
- begin
- if (reset)
- begin
- overrun <= 0;
- WR <= 0;
- rd_select <= 0;
- chan_rdreq <= 0;
- timestamp_complete <= 0;
- check_next <= 0;
- state <= `IDLE;
- end
- else case (state)
- `IDLE: begin
- chan_rdreq <= #1 0;
- //check if the channel is full
- if(~chan_empty[check_next])
- begin
- if (have_space)
- begin
- //transmit if the usb buffer have space
- //check if we should send
- if (ready_to_send)
- state <= #1 `HEADER1;
-
- overrun[check_next] <= 0;
- end
- else
- begin
- state <= #1 `IDLE;
- overrun[check_next] <= 1;
- end
- rd_select <= #1 check_next;
- end
- check_next <= #1 (check_next == channels ? 4'd0 : check_next +
4'd1);
- end
-
- `HEADER1: begin
- fifodata[`PAYLOAD_LEN] <= #1 9'd504;
- payload_len <= #1 9'd504;
- fifodata[`TAG] <= #1 0;
- fifodata[`MBZ] <= #1 0;
- WR <= #1 1;
-
- state <= #1 `HEADER2;
- read_length <= #1 0;
- end
-
- `HEADER2: begin
- fifodata[`CHAN] <= #1 true_channel;
- fifodata[`RSSI] <= #1 true_rssi[5:0];
- fifodata[`BURST] <= #1 0;
- fifodata[`DROPPED] <= #1 0;
- fifodata[`UNDERRUN] <= #1 (check_next == 0) ? 1'b0 :
underrun[true_channel];
- fifodata[`OVERRUN] <= #1 (check_next == 0) ? 1'b0 :
overrun[true_channel];
- state <= #1 `TIMESTAMP;
- end
-
- `TIMESTAMP: begin
- fifodata <= #1 (timestamp_complete ? timestamp_clock[31:16] :
timestamp_clock[15:0]);
- timestamp_complete <= #1 ~timestamp_complete;
-
- if (~timestamp_complete)
- chan_rdreq <= #1 1;
-
- state <= #1 (timestamp_complete ? `FORWARD : `TIMESTAMP);
- end
-
- `FORWARD: begin
- read_length <= #1 read_length + 9'd2;
- fifodata <= #1 (read_length >= payload_len ? 16'hDEAD :
chan_fifodata);
-
- if (read_length >= `MAXPAYLOAD)
- begin
- WR <= #1 0;
- state <= #1 `IDLE;
- chan_rdreq <= #1 0;
- end
- else if (read_length == payload_len - 4)
- chan_rdreq <= #1 0;
- end
-
- default: begin
- //handling error state
- state <= `IDLE;
- end
- endcase
- end
-endmodule
-
+// packet_builder.v
+//
+// Create packet outputs for a single channel.
+// 16 bit wide output, suitable for sending to FX2/USB.
+// Inputs include all header information and ADC data
+
+// It is assumed that the header inputs are valid
+// when rden is set, and during the first 4 clock
+// cycles while the header is being sent.
+// Depending on the architecture, external logic may be
+// required to capture and hold volitile values
+// such as timestamp during this period. The header_rd
+// line will be set when the header values can be released.
+
+// chan_data should be updated on every clock cyle as long
+// as chan_rd is set. It will read payload_length/2
+// (rounding up) times.
+
+// Output is limited to 256 reads per rden. rden must be
+// dropped between packets. This is mostly a workaround for
+// the FX2 257 RD bug.
+
+// Dependencies:
+// inband_packet_defs.v
+
+module packet_builder (
+ // Control / Status
+ input clk, //negedge
+ input rden, //read enable, resets state when clear
+
+ // Header inputs
+ output reg header_rd, //header_data read signal
TODO: ren header_ack
+
+ input overrun,
+ input underrun,
+ input dropped_packet,
+ input start_burst,
+ input end_burst,
+ input [5:0] rssi,
+ input [4:0] chan_number,
+ input [3:0] tag,
+ input [8:0] payload_length,
+ input [31:0] timestamp,
+
+ // ADC data
+ output reg chan_rd, //chan_data read signal
+ input [15:0] chan_data,
+
+ // Packet output
+ output reg [15:0] packet_data,
+ output reg packet_complete //raised on last output
+);
+
+ //main state var, our line position (16b wide) in the packet, +1 every
clk
+ reg [7:0] read_count;
+
+ reg [7:0] padding_pos; //read_count where padding starts
+
+ //Combinational logic
+
+ //Wire up inputs to mux the possible packet_data outputs
+ wire [15:0] h1,h2,ts1,ts2,pl_data; //header,timestamp,channel data
+
+ assign h1[`PAYLOAD_LEN] = payload_length;
+ assign h1[`TAG] = tag;
+ assign h1[`MBZ] = 0;
+
+ assign h2[`CHAN] = chan_number;
+ assign h2[`RSSI] = rssi;
+ assign h2[`BURST_START] = start_burst;
+ assign h2[`BURST_END] = end_burst;
+ assign h2[`DROPPED] = dropped_packet;
+ assign h2[`UNDERRUN] = underrun;
+ assign h2[`OVERRUN] = overrun;
+
+ assign ts1 = timestamp[15:0];
+ assign ts2 = timestamp[31:16];
+
+ //Select channel data or padding values
+ //NOTE: This will not mask the spare byte on odd payload sizes.
+ // It is assumed that it is not worth the trouble (no harm done).
+ // Really, the specifed pad value probably isn't required
either...
+ assign pl_data = chan_rd ? chan_data : `PAD_VALUE; //payload
or padding
+
+ //Select the proper output based on the read counter
+ always @* //unregistered, don't want clock delay
+ begin
+ case (read_count)
+ `RD_HEADER1: packet_data <= h1;
+ `RD_HEADER2: packet_data <= h2;
+ `RD_TIMESTAMP1: packet_data <= ts1;
+ `RD_TIMESTAMP2: packet_data <= ts2;
+ default: packet_data <= pl_data;
+ endcase
+ end
+
+ //Timing logic
+ always @(negedge clk) begin
+ if (!rden) begin
+ read_count <= `RD_HEADER1;
+ packet_complete <= 1'd0;
+ chan_rd <= 1'd0;
+ end
+ else begin
+ //save some state on the first clock
+ if (read_count == `RD_HEADER1) begin
+ //calculate when we should start sending padding
+ //since payload is specified in bytes, and data
out is 16b,
+ //we need to round up odd values
+ //FIXME: should we force a valid paylod size
here? We assume =< max
+ padding_pos <= (payload_length>>1) +
(payload_length[0] ? 8'd4 : 8'd3);
+ end
+
+ //handle packet complete
+ if (read_count == `RD_LAST) begin
+ chan_rd <= 1'b0;
+ packet_complete <= 1'b1;
+ //don't update the read_count, hold fast
+ end
+ else begin
+ //we want to read the channel in advance, while
sending ts2, so set
+ //chan_rd @ ts1 (t=2), then stop reading when
payload is sent / padding starts
+ chan_rd <= ((read_count > `RD_TIMESTAMP1) &&
(read_count < padding_pos)) ? 1'd1 : 1'd0;
+
+ packet_complete <= 1'b0;
+ read_count <= read_count + 8'd1;
+ end
+
+ end // else
+ end // always
+
+ //ack the header fifo when we are done w/ it
+ always @(negedge clk) begin
+ if (read_count == `RD_TIMESTAMP2) header_rd <= 1'd1;
+ else header_rd <= 1'd0;
+ end
+
+endmodule
+
Modified:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2008-09-07 06:36:29 UTC (rev 9515)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2008-09-07 08:20:22 UTC (rev 9516)
@@ -1,209 +1,359 @@
-//`include "../../firmware/include/fpga_regs_common.v"
-//`include "../../firmware/include/fpga_regs_standard.v"
-module rx_buffer_inband
- ( input usbclk,
- input bus_reset,
- input reset, // DSP side reset (used here), do not reset registers
- input reset_regs, //Only reset registers
- output [15:0] usbdata,
- input RD,
- output wire have_pkt_rdy,
- output reg rx_overrun,
- input wire [3:0] channels,
- input wire [15:0] ch_0,
- input wire [15:0] ch_1,
- input wire [15:0] ch_2,
- input wire [15:0] ch_3,
- input wire [15:0] ch_4,
- input wire [15:0] ch_5,
- input wire [15:0] ch_6,
- input wire [15:0] ch_7,
- input rxclk,
- input rxstrobe,
- input clear_status,
- input [6:0] serial_addr,
- input [31:0] serial_data,
- input serial_strobe,
- output wire [15:0] debugbus,
+// rx_buffer_inband
+//
+// This is the "pull" design, where packets are assembled as
+// they are read out of the usbdata bus by the FX2.
+//
+// Header information such as timestamp is saved in a seperate
+// FIFO that runs parallel to the channel data FIFO.
+// (see rx_channel_buffer.v)
+//
+// Note: the max input rate is master_clock/2 since the interleaving is
+// currently done on the front end. The data FIFOs could be widened
+// and interleaved by the packet builder to reach master_clock rates)
+// However, unless sampling relatively short bursts,this would eventually
+// overrun the FIFOs as the FX2 interface wouldn't be able to keep up.
+//
+// +---------+ |\
+// ch0_hdr ->| Channel |-> header ->| \
+// | Buffer | | \
+// ch0_data ->| |-> data --->| \ +---------+
+// +---------+ | M |->| Packet |
+// | U | | Builder |-> FX2
+// +---------+ | X |->| |
+// ch1_hdr ->| Channel |-> header ->| | +---------+
+// | Buffer | | /
+// ch1_data ->| |-> data --->| /
+// +---------+ |/
+//
+//
+// The control channel in this module is logically channel 0, where
+// it's packet channel ID is 0x1F. The logical data chans are chan+1.
+// This simplifies the generation logic with a parameterized number
+// of channels. (And priority)
+//
+// When there are multiple channels with complete packets with
+// usbdata to be sent, the lower logical channel is sent first.
+// (control is the highest priority)
+//
+// Dependencies:
+// inband_packet_defs.v
+// rx_channel_buffer.v
+// packet_builder.v
+//
+// TODO: handle single channel in dual chan config (channels input)
+// TODO: Refactor. This interface was kept from the original version.
+
+
+module rx_buffer_inband(
+ //control
+ input rxclk, //master clock
+ input reset, // DSP side reset (used here), do not reset registers
+ input reset_regs, //Only reset registers
+
+ //Channel inputs
+ input rxstrobe,
+ input [3:0] channels, //number of channels
(unused)
+ input [15:0] ch_0,
+ input [15:0] ch_1,
+ input [15:0] ch_2,
+ input [15:0] ch_3,
+ input [15:0] ch_4,
+ input [15:0] ch_5,
+ input [15:0] ch_6,
+ input [15:0] ch_7,
+ input wire [31:0] rssi_0,
+ input wire [31:0] rssi_1,
+ input wire [31:0] rssi_2,
+ input wire [31:0] rssi_3,
+
+ //FX2/USB interface
+ input usbclk,
+ input bus_reset,
+ input RD,
+ output [15:0] usbdata,
+ output have_pkt_rdy,
+ output rx_overrun,
+
+ //Serial / Command Bus //Unused?
+ input serial_strobe,
+ input clear_status,
+ input [6:0] serial_addr,
+ input [31:0] serial_data,
+
+ //Connection with tx_inband
+ input rx_WR,
+ input rx_WR_done,
+ input [15:0] rx_databus,
+ input wire [1:0] tx_underrun,
+ output rx_WR_enabled
+
+ /////////////////////
+ //Debug
+ ,output [15:0] debugbus
- //Connection with tx_inband
- input rx_WR,
- input [15:0] rx_databus,
- input rx_WR_done,
- output reg rx_WR_enabled,
- //signal strength
- input wire [31:0] rssi_0, input wire [31:0] rssi_1,
- input wire [31:0] rssi_2, input wire [31:0] rssi_3,
- input wire [1:0] tx_underrun
- );
-
- parameter NUM_CHAN = 1;
- genvar i ;
-
- // FX2 Bug Fix
- reg [8:0] read_count;
- always @(negedge usbclk)
- if(bus_reset)
- read_count <= #1 9'd0;
- else if(RD & ~read_count[8])
- read_count <= #1 read_count + 9'd1;
- else
- read_count <= #1 RD ? read_count : 9'b0;
-
- // Time counter
- reg [31:0] timestamp_clock;
- always @(posedge rxclk)
- if (reset)
- timestamp_clock <= 0;
- else
- timestamp_clock <= timestamp_clock + 1;
-
- // USB side fifo
- wire [11:0] rdusedw;
- wire [11:0] wrusedw;
- wire [15:0] fifodata;
- wire [15:0] fifodata_il[0:NUM_CHAN];
- wire WR;
- wire have_space;
- reg sel;
- reg wr;
+ //MUX,FX2
+ ,output [3:0] dbg_chan_sel
+ ,output dbg_switch_ok
+ ,output [6:0] dbg_num_pkt_0
+ ,output [6:0] dbg_num_pkt_1
+
+ //IQ interleaving
+ ,output dbg_rx_wren
+ ,output dbg_iq
- always@(posedge rxclk)
- begin
- if(reset)
- begin
- sel<=1;
- wr<=0;
- end
- else if(rxstrobe)
- begin
- sel<=0;
- wr<=1;
- end
- else if(wr&~sel)
- sel<=1;
- else if(wr&sel)
- wr<=0;
- else
- wr<=0;
- end
+ //chan buffer
+ ,output [6:0] ph_wrusedw_1
+ ,output ph_full_1
+ ,output [9:0] cd_wrusedw_1
+ ,output cd_full_1
+ ,output save_header_1
+ ,output rd_data_en_1
+ ,output [7:0] dbg_sample_counter_1
+
+);
+
+ parameter NUM_CHAN = 1;
+
+ genvar i;
- assign fifodata_il[0] = (sel)?ch_1:ch_0;
- assign fifodata_il[1] = (sel)?ch_3:ch_2;
+
/////////////////////////////////////////////////////////////////////////
+ // Debug assignments
- fifo_4kx16_dc rx_usb_fifo (
- .aclr ( reset ),
- .data ( fifodata ),
- .rdclk ( ~usbclk ),
- .rdreq ( RD & ~read_count[8] ),
- .wrclk ( rxclk ),
- .wrreq ( WR ),
- .q ( usbdata ),
- .rdempty ( ),
- .rdusedw ( rdusedw ),
- .wrfull ( ),
- .wrusedw ( wrusedw ) );
-
- assign have_pkt_rdy = (rdusedw >= 12'd256);
- assign have_space = (wrusedw < 12'd760);
-
- // Rx side fifos
- // These are of size [NUM_CHAN:0] because the extra channel is used for the
- // RX command channel. If there were no command channel, they would be
- // NUM_CHAN-1.
- wire chan_rdreq;
- wire [15:0] chan_fifodata;
- wire [9:0] chan_usedw;
- wire [NUM_CHAN:0] chan_empty;
- wire [3:0] rd_select;
- wire [NUM_CHAN:0] rx_full;
-
- packet_builder #(NUM_CHAN) rx_pkt_builer (
- .rxclk ( rxclk ),
- .reset ( reset ),
- .timestamp_clock ( timestamp_clock ),
- .channels ( NUM_CHAN ),
- .chan_rdreq ( chan_rdreq ),
- .chan_fifodata ( chan_fifodata ),
- .chan_empty ( chan_empty ),
- .rd_select ( rd_select ),
- .chan_usedw ( chan_usedw ),
- .WR ( WR ),
- .fifodata ( fifodata ),
- .have_space ( have_space ),
- .rssi_0(rssi_0), .rssi_1(rssi_1),
- .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug),
- .underrun(tx_underrun));
-
- // Detect overrun
- always @(posedge rxclk)
- if(reset)
- rx_overrun <= 1'b0;
- else if(rx_full[0])
- rx_overrun <= 1'b1;
- else if(clear_status)
- rx_overrun <= 1'b0;
+ assign debugbus = 32'h0;
+
+ //IQ interleaving
+ assign dbg_rx_wren = rx_wren;
+ assign dbg_iq = iq;
-
- // FIXME: what is the purpose of these two lines?
- wire [15:0]ch[NUM_CHAN:0];
- assign ch[0] = ch_0;
+ //MUX
+ assign dbg_chan_sel = chan_sel;
+ assign dbg_switch_ok = switch_ok;
+ assign dbg_num_pkt_0 = num_pkt[0];
+ assign dbg_num_pkt_1 = num_pkt[1];
- wire cmd_empty;
+ //Channel Buffers
+ wire [6:0] dbg_ph_wrusedw[NUM_CHAN:0];
+ wire [9:0] dbg_cd_wrusedw[NUM_CHAN:0];
+ wire dbg_ph_full[NUM_CHAN:0];
+ wire dbg_cd_full[NUM_CHAN:0];
+ wire dbg_save_header[NUM_CHAN:0];
+ wire [7:0] dbg_sample_counter[NUM_CHAN:0];
- always @(posedge rxclk)
- if(reset)
- rx_WR_enabled <= 1;
- else if(cmd_empty)
- rx_WR_enabled <= 1;
- else if(rx_WR_done)
- rx_WR_enabled <= 0;
+ assign ph_wrusedw_1 = dbg_ph_wrusedw[1];
+ assign cd_wrusedw_1 = dbg_cd_wrusedw[1];
+ assign ph_full_1 = dbg_ph_full[1];
+ assign cd_full_1 = dbg_cd_full[1];
+ assign save_header_1 = dbg_save_header[1];
+ assign rd_data_en_1 = data_rd[1];
+ assign dbg_sample_counter_1 = dbg_sample_counter[1];
+
+
/////////////////////////////////////////////////////////////////////////
+ // Internal timestamp counter
+ // TODO: this should be external and shared w/ tx
+ reg [31:0] timestamp_counter;
+
+ always @ (posedge rxclk) begin
+ if (reset)
+ timestamp_counter <= 32'd0;
+ else
+ timestamp_counter <= timestamp_counter + 32'd1;
+ end
+
+
/////////////////////////////////////////////////////////////////////////
+ // Wiring for the channel buffers
+ // IQ interleaving
+ reg iq; //select I or Q
+ wire rx_wren; //Channel buffer write signal
- // Of Size 0:NUM_CHAN due to extra command channel.
- wire [15:0] dataout [0:NUM_CHAN];
- wire [9:0] usedw [0:NUM_CHAN];
- wire empty[0:NUM_CHAN];
+ always @ (posedge rxclk)
+ iq = rx_wren ? ~iq : 1'b0;
+
+ assign rx_wren = ~reset & ( rxstrobe | iq);
+
+ // select the data inputs for each channel
+ wire [15:0] i_chan_data[4:0];
- generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
- begin : generate_channel_fifos
+ assign i_chan_data[0] = rx_databus; //control data
+ assign i_chan_data[1] = iq ? ch_1 : ch_0;
+ assign i_chan_data[2] = iq ? ch_3 : ch_2;
+ assign i_chan_data[3] = iq ? ch_5 : ch_4;
+ assign i_chan_data[4] = iq ? ch_7 : ch_6;
+
+ wire [5:0] i_rssi[4:0];
+ assign i_rssi[0] = rssi_0[5:0];
+ assign i_rssi[1] = rssi_1[5:0];
+ assign i_rssi[2] = rssi_2[5:0];
+ assign i_rssi[3] = rssi_3[5:0];
- wire rdreq;
+ //misc control channel
+ assign rx_WR_enabled = 1'd1; //we are always ready. TODO: Ok?
+
+ //declare nets to be assigned by generate below
+ wire i_wren[0:NUM_CHAN];
+ wire i_flush[0:NUM_CHAN];
- assign rdreq = (rd_select == i) & chan_rdreq;
+ reg [6:0] num_pkt[0:NUM_CHAN];
- fifo_1kx16 rx_chan_fifo (
- .aclr ( reset ),
- .clock ( rxclk ),
- .data ( fifodata_il[i] ),
- .rdreq ( rdreq ),
- .wrreq ( ~rx_full[i] & wr),
- .empty (empty[i]),
- .full (rx_full[i]),
- .q ( dataout[i]),
- .usedw ( usedw[i]),
- .almost_empty(chan_empty[i])
- );
- end
- endgenerate
+ wire [63:0] i_header_data[0:NUM_CHAN];
+
+ wire header_rd[0:NUM_CHAN];
+ wire data_rd[0:NUM_CHAN];
+
+ wire [63:0] o_header_data[0:NUM_CHAN];
+ wire [15:0] o_chan_data[0:NUM_CHAN];
+
+ wire [3:0] pri_chan[0:NUM_CHAN];
+
+ //collect ready sigs for global pkt ready
+ wire [0:NUM_CHAN] chans_ready;
+ assign have_pkt_rdy = chans_ready ? 1'd1 : 1'd0;
+
+ //overrun signals
+ wire [NUM_CHAN:0] overrun;
+ assign rx_overrun = overrun == 0 ? 1'b0 : 1'b1;
+
+
/////////////////////////////////////////////////////////////////////////
+ // Process command data from tx / cmd_reader
+ // We need to work with the rx_WR/rx_WR_done signals to make them
+ // compatible with rx_channel_buffer.
+ reg cmd_flush,have_wr;
- wire [7:0] debug;
-
- fifo_1kx16 rx_cmd_fifo (
- .aclr ( reset ),
- .clock ( rxclk ),
- .data ( rx_databus ),
- .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ),
- .wrreq ( rx_WR & rx_WR_enabled),
- .empty ( cmd_empty),
- .full ( rx_full[NUM_CHAN] ),
- .q ( dataout[NUM_CHAN]),
- .usedw ( usedw[NUM_CHAN] )
- );
+ always @ (posedge rxclk)
+ begin
+ if (reset) cmd_flush <= 1'b0;
+ else begin
+ if (rx_WR) have_wr <= 1'b1;
+
+ if (rx_WR_done & have_wr) begin
+ cmd_flush <= 1'b1;
+ have_wr <= 1'b0;
+ end
+ else cmd_flush <= 1'b0;
+ end
+ end
- assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
- assign chan_fifodata = dataout[rd_select];
- assign chan_usedw = usedw[rd_select];
- assign debugbus = {4'd0, rxclk, rxstrobe, rx_full[0], rx_full[1], sel, wr};
+
+
/////////////////////////////////////////////////////////////////////////
+ // Generate the individual channel buffers
+
+ generate for (i=0; i <= NUM_CHAN; i=i+1)
+ begin : cb
-endmodule
+ assign chans_ready[i] = num_pkt[i] ? 1'd1 : 1'd0;
+
+ //channel selection ( 0 > 1 > 2 ... )
+ if (i != NUM_CHAN) assign pri_chan[i] = chans_ready[i] ? i :
pri_chan[i+1];
+ else assign pri_chan[i] = chans_ready[i] ? i : 5'd0;
+
+ //the control channel (0) is connected differently
+ //TODO: maybe this should just be broken out for clarity
+ if (i == 0) begin
+ assign i_wren[i] = rx_WR;
+ assign i_flush[i] = cmd_flush;
+ assign i_header_data[i][`CB_CHAN] = 5'h1f;
+ assign i_header_data[i][`CB_RSSI] = 6'd0;
+ assign i_header_data[i][`CB_UNDERRUN] = 1'b0;
+ end
+ else begin
+ assign i_wren[i] = rx_wren;
+ assign i_flush[i] = 1'd0;
+ assign i_header_data[i][`CB_CHAN] = i-1;
+ assign i_header_data[i][`CB_RSSI] = i_rssi[i-1];
+ assign i_header_data[i][`CB_UNDERRUN] =
tx_underrun[i-1];
+ end
+
+ assign i_header_data[i][`CB_OVERRUN] = 1'b0; //generated in
channel_buffer
+ assign i_header_data[i][`CB_PAYLOAD_LEN] = 9'd0; //not
currently an input (auto-generated)
+ assign i_header_data[i][`CB_TIMESTAMP] = timestamp_counter;
+ assign i_header_data[i][`CB_TIMESTAMP] = timestamp_counter;
+
+ assign i_header_data[i][`CB_NON_INPUTS] = 0;
+
+ //control signals from mux
+ assign header_rd[i] = chan_sel == i ? mux_header_rd : 1'd0;
+ assign data_rd[i] = chan_sel == i ? mux_chan_rd : 1'd0;
+
+ rx_channel_buffer chan_buf[i] (
+ .reset (reset),
+
+ .wrclk (rxclk),
+ .wren (i_wren[i]),
+ .flush_packet (i_flush[i]),
+
+ .rdclk (usbclk),
+ .rd_data_en (data_rd[i]),
+ .rd_header_en (header_rd[i]),
+ .num_packets (num_pkt[i]),
+ .overrun(overrun[i]),
+
+ .i_chan_data (i_chan_data[i]),
+ .i_header_data (i_header_data[i]),
+ .o_chan_data (o_chan_data[i]),
+ .o_header_data (o_header_data[i])
+
+ //debug
+ ,.dbg_ph_wrusedw(dbg_ph_wrusedw[i])
+ ,.dbg_cd_wrusedw(dbg_cd_wrusedw[i])
+ ,.dbg_ph_full(dbg_ph_full[i])
+ ,.dbg_cd_full(dbg_cd_full[i])
+ ,.dbg_save_header(dbg_save_header[i])
+ ,.dbg_sample_counter(dbg_sample_counter[i])
+ );
+
+ end
+ endgenerate
+
+
/////////////////////////////////////////////////////////////////////////
+ // Channel Muxer / Selector
+
+ wire pkt_complete; //from packet builder
+ reg [3:0] chan_sel; //the selected channel
+
+ //Mux output values
+ wire mux_header_rd;
+ wire [63:0] mux_header_data;
+ wire mux_chan_rd;
+ wire [15:0] mux_chan_data;
+
+ //map data outputs
+ assign mux_header_data = o_header_data[chan_sel];
+ assign mux_chan_data = o_chan_data[chan_sel];
+
+ wire switch_ok;
+ assign switch_ok = !RD || pkt_complete;
+
+ // Handle channel mux selection on usbclk.
+ // Only change when when no packet is being sent
+ always @ (negedge usbclk)
+ begin
+ if (switch_ok) chan_sel <= pri_chan[0];
+ end //always
+
+
/////////////////////////////////////////////////////////////////////////
+ // Packet Builder
+ packet_builder pb (
+ // Control / Status
+ .clk (usbclk),
+ .rden (RD),
+
+ .header_rd (mux_header_rd),
+ .overrun (mux_header_data[`CB_OVERRUN]),
+ .underrun (mux_header_data[`CB_UNDERRUN]),
+ .dropped_packet (mux_header_data[`CB_DROPPED]),
+ .start_burst (mux_header_data[`CB_BURST_START]),
+ .end_burst (mux_header_data[`CB_BURST_END]),
+ .rssi (mux_header_data[`CB_RSSI]),
+ .chan_number (mux_header_data[`CB_CHAN]),
+ .tag (mux_header_data[`CB_TAG]),
+ .payload_length (mux_header_data[`CB_PAYLOAD_LEN]),
+ .timestamp (mux_header_data[`CB_TIMESTAMP]),
+
+ .chan_rd (mux_chan_rd),
+ .chan_data (mux_chan_data),
+
+ .packet_data (usbdata),
+ .packet_complete (pkt_complete) //raised on last output
+ );
+
+endmodule
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_channel_buffer.v
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_channel_buffer.v
(rev 0)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_channel_buffer.v
2008-09-07 08:20:22 UTC (rev 9516)
@@ -0,0 +1,173 @@
+// rx_channel_buffer
+// This module encapsulates the buffering for a single channel,
+// including timestamp/header sampling and variable payload
+// length packet generation.
+//
+// Header information such as timestamp is saved in a seperate
+// FIFO that runs parallel to the channel data FIFO.
+//
+// Header information is captured with the first sample of a
+// packet, but is pushed to the FIFO after the packet's chan data.
+// This permits such things as variable size packets without having
+// to know the size at the time of the first sample. This is
+// used for the control channel and in overrun conditions.
+//
+// NOTE: The FIFOS used are dual clock, WITH look ahead, so
+// rd_req is asserted AFTER the read (it is an ACK). This
+// helps us with the FX2 RD/usbdata timing.
+//
+// Dependencies:
+// inband_packet_defs.v
+// fifo_128x64_dc_la.v
+// fifo_1kx16_dc_la.v
+
+
+module rx_channel_buffer (
+ input reset,
+
+ //Input control
+ input wrclk,
+ input wren,
+ input flush_packet, //will send non-full packet
+
+ //Input
+ input [15:0] i_chan_data,
+ input [63:0] i_header_data,
+
+ //Output control
+ input rdclk, //negedge
+ input rd_data_en,
+ input rd_header_en,
+
+ //Status
+ output [6:0] num_packets, //Number of packets ready to go
+ output reg overrun,
+
+ //Output
+ output [15:0] o_chan_data,
+ output [63:0] o_header_data
+
+ //Debug
+ ,output [7:0] dbg_sample_counter
+ ,output [6:0] dbg_ph_wrusedw
+ ,output [9:0] dbg_cd_wrusedw
+ ,output dbg_ph_full,dbg_cd_full,dbg_save_header
+);
+
+ parameter SAMP_PER_PKT = 252; //16 bit samples
+
+ parameter CD_FIFO_SIZE = 1024; //Depth of channel data fifo
+
+ //don't know if this is possible, it would be nice
+ //parameter CD_FIFO_NAME = "fifo_1kx16"; //channel data fifo
implementation name
+
+ //debug
+ assign dbg_save_header = save_header;
+ assign dbg_ph_full = ph_full;
+ assign dbg_cd_full = cd_full;
+ assign dbg_cd_wrusedw = cd_wrusedw;
+ assign dbg_sample_counter = sample_counter;
+
+ // Temporary header info, prior to being pushed to fifo
+ reg [63:0] temp_header;
+
+ // Packet header fifo related
+ wire ph_full;
+
+ fifo_128x64_dc_la ph_fifo (
+ .aclr (reset),
+// .data (ph_fifo_input),
+ .data (temp_header),
+ .wrclk (wrclk),
+ .wrreq (save_header),
+ .wrfull (ph_full),
+ .rdclk (~rdclk), //negedge
+ .rdreq (rd_header_en),
+ .rdusedw(num_packets),
+ .q (o_header_data)
+ //debug
+ ,.wrusedw (dbg_ph_wrusedw)
+
+ );
+
+ //
+ //Channel data fifo related
+ wire [9:0] cd_wrusedw;
+ wire cd_full;
+
+ fifo_1kx16_dc_la cd_fifo (
+ .aclr ( reset ),
+ .data ( i_chan_data ),
+// .data ( temp_data ),
+ .wrclk (wrclk),
+ .wrreq (wren & ~overrun), //block on overrun
+ .wrfull (cd_full),
+ .wrusedw (cd_wrusedw),
+ .rdclk (~rdclk), //negedge
+ .rdreq (rd_data_en),
+ .q (o_chan_data)
+ //debug
+ //,.rdusedw (cd_rdusedw)
+ );
+
+
/////////////////////////////////////////////////////////////////////////
+ // Sampling and overrun logic
+ // Keep track of how many samples we have saved so we can save header
+ // info at the right time.
+ //
+ // Overrun behavior is to fill the data fifo until full, at which
+ // time the header is pushed with the current payload size and the
+ // ovverrun bit set. Sampling is suspended until there is room for
+ // a complete packet. If the header fifo is full (unlikely, and which
+ // would happen after completing a packet), sampling is suspended.
+ // In any case, all samples in a packet should be contiguous.
+
+ reg [7:0] sample_counter;
+ reg save_header; //temp->fifo on this signal
+ reg do_flush; //internal signal to force a packet
+
+ always @ ( posedge wrclk ) begin
+ if (reset) begin
+ save_header <= 1'b0;
+ overrun = 1'b0;
+ sample_counter = 8'd0;
+ do_flush = 1'b0;
+ end
+ else begin
+ //Overrun logic
+ if (ph_full | cd_full) begin
+ if (~overrun & ~ph_full) //only flush
header once
+ do_flush = 1'b1;
+
+ overrun = 1'b1;
+ end
+ else if (overrun & ~ph_full & (cd_wrusedw <
(CD_FIFO_SIZE - SAMP_PER_PKT)))
+ overrun = 1'b0;
+
+ if (flush_packet)
+ do_flush = 1'b1;
+
+ //Only sample on wren
+ if (wren && !overrun) begin //new channel data
+ //if this is first sample, save the header info
(incl timestamp)
+ if (!sample_counter) temp_header <=
i_header_data;
+
+ sample_counter = sample_counter + 8'd1;
//blocking assign, we want new val now for size
+ end
+
+ //If done w/ packet (full or flush), then save the
header info to fifo
+ if (do_flush || (sample_counter == SAMP_PER_PKT)) begin
+ //update some header values before pushing onto
the fifo
+ temp_header[`CB_PAYLOAD_LEN] <=
(sample_counter<<1); //actual payload length (x2 bytes)
+ temp_header[`CB_OVERRUN] <= overrun;
+
+ save_header <= 1'b1; //wren for header fifo
+ sample_counter = 8'd0; //start counting new
packet
+ do_flush = 1'b0;
+ end
+ else
+ save_header <= 1'b0;
+ end //else
+ end //always
+
+endmodule
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.qpf
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.qpf
(rev 0)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.qpf
2008-09-07 08:20:22 UTC (rev 9516)
@@ -0,0 +1,23 @@
+# Copyright (C) 1991-2008 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+
+
+QUARTUS_VERSION = "8.0"
+DATE = "13:30:17 August 27, 2008"
+
+
+# Revisions
+
+PROJECT_REVISION = "rx_buffer_inband_tb"
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.qsf
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.qsf
(rev 0)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.qsf
2008-09-07 08:20:22 UTC (rev 9516)
@@ -0,0 +1,46 @@
+# Copyright (C) 1991-2008 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+# rx_buffer_inband_tb_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+# assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY Cyclone
+set_global_assignment -name DEVICE EP1C20F400C6
+set_global_assignment -name TOP_LEVEL_ENTITY rx_buffer_inband_tb
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "8.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:29:11 SEPTEMBER
06, 2008"
+set_global_assignment -name LAST_QUARTUS_VERSION "8.0 SP1"
+set_global_assignment -name VERILOG_FILE ../inband_packet_defs.v
+set_global_assignment -name VERILOG_FILE ../../megacells/fifo_128x64_dc_la.v
+set_global_assignment -name VERILOG_FILE ../../megacells/fifo_1kx16_dc_la.v
+set_global_assignment -name VERILOG_FILE ../packet_builder.v
+set_global_assignment -name VERILOG_FILE ../rx_buffer_inband.v
+set_global_assignment -name VERILOG_FILE ../rx_channel_buffer.v
+set_global_assignment -name VERILOG_FILE rx_buffer_inband_tb.v
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to |
-section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name SIMULATION_MODE FUNCTIONAL
+set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE
rx_buffer_inband_tb.vwf
\ No newline at end of file
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.v
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.v
(rev 0)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.v
2008-09-07 08:20:22 UTC (rev 9516)
@@ -0,0 +1,235 @@
+// rx_buffer_inband_tb
+
+// This "test bench" is actually run in quartus as a top-level module
+// Basically just to reduce the pin-count from rx_buffer_inband for the fitter.
+
+module rx_buffer_inband_tb (
+ //General
+ input clk,
+ input reset,
+ input reset_regs,
+
+ output reg [31:0] timestamp,
+
+ //Channel inputs
+ input wire rxstrobe,
+ output wire [15:0] chan_data_0,
+ //output wire [15:0] chan_data_1,
+ //output wire [15:0] chan_data_2,
+ //output wire [15:0] chan_data_3,
+
+ //tx_buffer interconnection
+ output reg rx_WR,
+ output reg rx_WR_done,
+ output wire rx_WR_enabled,
+ output reg [15:0] rx_databus,
+ output reg [1:0] tx_underrun,
+
+ //FX2 interface
+ input wire usbclk,
+ output wire usb_reset,
+ output reg usb_rd,
+ output wire usb_pkt_rdy,
+ output wire rx_overrun,
+ output wire [15:0] usb_data
+
+ //Debug
+ /////////////////////
+ //Debug
+
+ //MUX,FX2
+ ,output [3:0] dbg_chan_sel
+ ,output dbg_switch_ok
+ ,output [6:0] dbg_num_pkt_0
+ ,output [6:0] dbg_num_pkt_1
+
+ //IQ interleaving
+ ,output dbg_rx_wren
+ ,output dbg_iq
+
+ //chan buffer
+ ,output [6:0] ph_wrusedw_1
+ ,output ph_full_1
+ ,output [9:0] cd_wrusedw_1
+ ,output cd_full_1
+ ,output save_header_1
+ ,output rd_data_en_1
+ ,output [7:0] dbg_sample_counter_1
+);
+
+
+ //Channel inputs
+ wire [3:0] num_chan;
+ assign num_chan = 4'd2;
+
+ wire [15:0] chan_data_1;
+ wire [15:0] chan_data_2;
+ wire [15:0] chan_data_3;
+
+ wire [31:0] chan_rssi_0;
+ wire [31:0] chan_rssi_1;
+ assign chan_rssi_0 = 32'h00000000;
+ assign chan_rssi_1 = 32'h00000000;
+
+ //FX2
+ //assign usbclk = clk;
+
+ //Serial inferface
+ reg serial_strobe, clear_status;
+ reg [6:0] serial_addr;
+ reg [31:0] serial_data;
+
+
+ rx_buffer_inband rx_buffer (
+ //control
+ .rxclk(clk), //master clock
+ .reset(reset), // DSP side reset (used here), do not reset
registers
+ .reset_regs(reset_regs), //Only reset registers
+
+ //Channel inputs
+ .rxstrobe(rxstrobe),
+ .channels(num_chan),
+ .ch_0(chan_data_0),
+ .ch_1(chan_data_1),
+ .ch_2(chan_data_2),
+ .ch_3(chan_data_3),
+
+ .rssi_0(chan_rssi_0),
+ .rssi_1(chan_rssi_1),
+
+ //FX2/USB interface
+ .usbclk(usbclk),
+ .bus_reset(usb_reset),
+ .RD(usb_rd),
+ .usbdata(usb_data),
+ .have_pkt_rdy(usb_pkt_rdy),
+ .rx_overrun(rx_overrun),
+
+ //Serial / Command Bus
+ .serial_strobe(serial_strobe),
+ .clear_status(clear_status),
+ .serial_addr(serial_addr),
+ .serial_data(serial_data),
+
+ //Connection with tx_inband
+ .rx_WR(rx_WR),
+ .rx_WR_done(rx_WR_done),
+ .rx_databus(rx_databus),
+ .tx_underrun(tx_underrun),
+ .rx_WR_enabled(rx_WR_enabled)
+
+ //Debug
+ ,.dbg_chan_sel(dbg_chan_sel)
+ ,.dbg_switch_ok(dbg_switch_ok)
+ ,.dbg_num_pkt_0(dbg_num_pkt_0)
+ ,.dbg_num_pkt_1(dbg_num_pkt_1)
+
+ ,.dbg_rx_wren(dbg_rx_wren)
+ ,.dbg_iq(dbg_iq)
+
+ ,.ph_wrusedw_1(ph_wrusedw_1)
+ ,.cd_wrusedw_1(cd_wrusedw_1)
+ ,.ph_full_1(ph_full_1)
+ ,.cd_full_1(cd_full_1)
+ ,.save_header_1(save_header_1)
+ ,.rd_data_en_1(rd_data_en_1)
+ ,.dbg_sample_counter_1(dbg_sample_counter_1)
+ );
+
+ defparam rx_buffer.NUM_CHAN=1;
+
+ /////////////////////////////////////////////
+ //generate timestamp
+ always @ (posedge clk)
+ begin
+ if (reset) timestamp <= 32'd0;
+ else timestamp <= timestamp + 32'd1;
+ end
+
+ /////////////////////////////////////////////
+ //generate sawtooth channel input from timestamp
+ //assign chan_data_0 = {4'h0,timestamp[11:0]};
+ //assign chan_data_1 = {4'h1,timestamp[11:0]};
+ //assign chan_data_2 = {4'h2,timestamp[11:0]};
+ //assign chan_data_3 = {4'h3,timestamp[11:0]};
+
+ // div 2 should align w/ sample count
+ assign chan_data_0 = {4'h0,timestamp[12:1]};
+ assign chan_data_1 = {4'h1,timestamp[12:1]};
+ assign chan_data_2 = {4'h2,timestamp[12:1]};
+ assign chan_data_3 = {4'h3,timestamp[12:1]};
+
+ /////////////////////////////////////////////
+ // Control channel
+
+ reg [7:0] ctl_cnt;
+ reg do_ctl;
+
+ always @ (posedge clk)
+ begin
+ if (reset) begin
+ do_ctl <= 1'd0;
+ ctl_cnt <= 8'd0;
+ end
+
+ //when to send control data
+ if (timestamp == 32'd20) do_ctl <= 1'd1;
+
+ if (do_ctl) begin
+ ctl_cnt <= ctl_cnt + 8'd1;
+
+ case (ctl_cnt)
+ 8'd0: begin
+ rx_WR <= 1'd1;
+ rx_databus <= 16'h1234;
+ end
+ 8'd1: begin
+ rx_WR <= 1'd1;
+ rx_databus <= 16'h5678;
+ end
+ 8'd2: begin
+ rx_WR <= 1'd0;
+ rx_WR_done <= 1'd1;
+ end
+ default: begin
+ rx_WR <= 1'd0;
+ rx_WR_done <= 1'd0;
+ ctl_cnt <= 8'd0;
+ do_ctl <= 1'd0;
+ end
+ endcase
+ end
+ end
+
+
+
+ /////////////////////////////////////////////
+ //control FX2 reads
+`define FX2_PKT_READS 9'd257
+
+`define FX2_BEGIN_AT 32'h00000000
+//`define FX2_BEGIN_AT 32'h00000806
+
+ assign usb_reset = reset;
+
+ reg [8:0] usb_counter;
+
+ always @ (negedge usbclk)
+ begin
+ if (reset) begin
+ usb_counter <= 9'd0;
+ usb_rd <= 1'd0;
+ end
+ else begin
+ if (usb_pkt_rdy && (timestamp >= `FX2_BEGIN_AT ) )
usb_rd <= 1'd1;
+
+ if (usb_rd) usb_counter = usb_counter + 9'd1;
+
+ if (usb_counter >= `FX2_PKT_READS) begin
+ usb_rd <= 1'd0;
+ usb_counter <= 9'd0;
+ end
+ end
+ end
+
+endmodule
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.vwf
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.vwf
(rev 0)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.vwf
2008-09-07 08:20:22 UTC (rev 9516)
@@ -0,0 +1,4718 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+*/
+
+HEADER
+{
+ VERSION = 1;
+ TIME_UNIT = ns;
+ DATA_OFFSET = 0.0;
+ DATA_DURATION = 50000.0;
+ SIMULATION_TIME = 0.0;
+ GRID_PHASE = 0.0;
+ GRID_PERIOD = 10.0;
+ GRID_DUTY_CYCLE = 50;
+}
+
+SIGNAL("clk")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "";
+}
+
+SIGNAL("chan_data_0")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = BUS;
+ WIDTH = 16;
+ LSB_INDEX = 0;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("chan_data_0[15]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "chan_data_0";
+}
+
+SIGNAL("chan_data_0[14]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "chan_data_0";
+}
+
+SIGNAL("chan_data_0[13]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "chan_data_0";
+}
+
+SIGNAL("chan_data_0[12]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "chan_data_0";
+}
+
+SIGNAL("chan_data_0[11]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "chan_data_0";
+}
+
+SIGNAL("chan_data_0[10]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "chan_data_0";
+}
+
+SIGNAL("chan_data_0[9]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "chan_data_0";
+}
+
+SIGNAL("chan_data_0[8]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "chan_data_0";
+}
+
+SIGNAL("chan_data_0[7]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "chan_data_0";
+}
+
+SIGNAL("chan_data_0[6]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "chan_data_0";
+}
+
+SIGNAL("chan_data_0[5]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "chan_data_0";
+}
+
+SIGNAL("chan_data_0[4]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "chan_data_0";
+}
+
+SIGNAL("chan_data_0[3]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "chan_data_0";
+}
+
+SIGNAL("chan_data_0[2]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "chan_data_0";
+}
+
+SIGNAL("chan_data_0[1]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "chan_data_0";
+}
+
+SIGNAL("chan_data_0[0]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "chan_data_0";
+}
+
+SIGNAL("rxstrobe")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "";
+}
+
+SIGNAL("reset")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "";
+}
+
+SIGNAL("reset_regs")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "";
+}
+
+SIGNAL("usbclk")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "";
+}
+
+SIGNAL("timestamp")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = BUS;
+ WIDTH = 32;
+ LSB_INDEX = 0;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("timestamp[31]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[30]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[29]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[28]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[27]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[26]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[25]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[24]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[23]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[22]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[21]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[20]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[19]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[18]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[17]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[16]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[15]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[14]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[13]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[12]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[11]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[10]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[9]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[8]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[7]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[6]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[5]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[4]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[3]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[2]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[1]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("timestamp[0]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "timestamp";
+}
+
+SIGNAL("cd_full_1")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("cd_wrusedw_1")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = BUS;
+ WIDTH = 10;
+ LSB_INDEX = 0;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("cd_wrusedw_1[9]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "cd_wrusedw_1";
+}
+
+SIGNAL("cd_wrusedw_1[8]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "cd_wrusedw_1";
+}
+
+SIGNAL("cd_wrusedw_1[7]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "cd_wrusedw_1";
+}
+
+SIGNAL("cd_wrusedw_1[6]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "cd_wrusedw_1";
+}
+
+SIGNAL("cd_wrusedw_1[5]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "cd_wrusedw_1";
+}
+
+SIGNAL("cd_wrusedw_1[4]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "cd_wrusedw_1";
+}
+
+SIGNAL("cd_wrusedw_1[3]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "cd_wrusedw_1";
+}
+
+SIGNAL("cd_wrusedw_1[2]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "cd_wrusedw_1";
+}
+
+SIGNAL("cd_wrusedw_1[1]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "cd_wrusedw_1";
+}
+
+SIGNAL("cd_wrusedw_1[0]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "cd_wrusedw_1";
+}
+
+SIGNAL("dbg_chan_sel")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = BUS;
+ WIDTH = 4;
+ LSB_INDEX = 0;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("dbg_chan_sel[3]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dbg_chan_sel";
+}
+
+SIGNAL("dbg_chan_sel[2]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dbg_chan_sel";
+}
+
+SIGNAL("dbg_chan_sel[1]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dbg_chan_sel";
+}
+
+SIGNAL("dbg_chan_sel[0]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dbg_chan_sel";
+}
+
+SIGNAL("dbg_iq")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("dbg_num_pkt_0")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = BUS;
+ WIDTH = 7;
+ LSB_INDEX = 0;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("dbg_num_pkt_0[6]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dbg_num_pkt_0";
+}
+
+SIGNAL("dbg_num_pkt_0[5]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dbg_num_pkt_0";
+}
+
+SIGNAL("dbg_num_pkt_0[4]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dbg_num_pkt_0";
+}
+
+SIGNAL("dbg_num_pkt_0[3]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dbg_num_pkt_0";
+}
+
+SIGNAL("dbg_num_pkt_0[2]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dbg_num_pkt_0";
+}
+
+SIGNAL("dbg_num_pkt_0[1]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dbg_num_pkt_0";
+}
+
+SIGNAL("dbg_num_pkt_0[0]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dbg_num_pkt_0";
+}
+
+SIGNAL("dbg_num_pkt_1")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = BUS;
+ WIDTH = 7;
+ LSB_INDEX = 0;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("dbg_num_pkt_1[6]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dbg_num_pkt_1";
+}
+
+SIGNAL("dbg_num_pkt_1[5]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dbg_num_pkt_1";
+}
+
+SIGNAL("dbg_num_pkt_1[4]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dbg_num_pkt_1";
+}
+
+SIGNAL("dbg_num_pkt_1[3]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dbg_num_pkt_1";
+}
+
+SIGNAL("dbg_num_pkt_1[2]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dbg_num_pkt_1";
+}
+
+SIGNAL("dbg_num_pkt_1[1]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dbg_num_pkt_1";
+}
+
+SIGNAL("dbg_num_pkt_1[0]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dbg_num_pkt_1";
+}
+
+SIGNAL("dbg_rx_wren")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("dbg_switch_ok")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("ph_full_1")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("rd_data_en_1")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("rx_WR")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("rx_WR_done")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("rx_WR_enabled")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("rx_databus")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = BUS;
+ WIDTH = 16;
+ LSB_INDEX = 0;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("rx_databus[15]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "rx_databus";
+}
+
+SIGNAL("rx_databus[14]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "rx_databus";
+}
+
+SIGNAL("rx_databus[13]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "rx_databus";
+}
+
+SIGNAL("rx_databus[12]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "rx_databus";
+}
+
+SIGNAL("rx_databus[11]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "rx_databus";
+}
+
+SIGNAL("rx_databus[10]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "rx_databus";
+}
+
+SIGNAL("rx_databus[9]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "rx_databus";
+}
+
+SIGNAL("rx_databus[8]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "rx_databus";
+}
+
+SIGNAL("rx_databus[7]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "rx_databus";
+}
+
+SIGNAL("rx_databus[6]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "rx_databus";
+}
+
+SIGNAL("rx_databus[5]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "rx_databus";
+}
+
+SIGNAL("rx_databus[4]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "rx_databus";
+}
+
+SIGNAL("rx_databus[3]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "rx_databus";
+}
+
+SIGNAL("rx_databus[2]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "rx_databus";
+}
+
+SIGNAL("rx_databus[1]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "rx_databus";
+}
+
+SIGNAL("rx_databus[0]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "rx_databus";
+}
+
+SIGNAL("rx_overrun")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("save_header_1")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("usb_data")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = BUS;
+ WIDTH = 16;
+ LSB_INDEX = 0;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("usb_data[15]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "usb_data";
+}
+
+SIGNAL("usb_data[14]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "usb_data";
+}
+
+SIGNAL("usb_data[13]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "usb_data";
+}
+
+SIGNAL("usb_data[12]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "usb_data";
+}
+
+SIGNAL("usb_data[11]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "usb_data";
+}
+
+SIGNAL("usb_data[10]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "usb_data";
+}
+
+SIGNAL("usb_data[9]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "usb_data";
+}
+
+SIGNAL("usb_data[8]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "usb_data";
+}
+
+SIGNAL("usb_data[7]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "usb_data";
+}
+
+SIGNAL("usb_data[6]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "usb_data";
+}
+
+SIGNAL("usb_data[5]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "usb_data";
+}
+
+SIGNAL("usb_data[4]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "usb_data";
+}
+
+SIGNAL("usb_data[3]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "usb_data";
+}
+
+SIGNAL("usb_data[2]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "usb_data";
+}
+
+SIGNAL("usb_data[1]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "usb_data";
+}
+
+SIGNAL("usb_data[0]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "usb_data";
+}
+
+SIGNAL("usb_rd")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("usb_reset")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("ph_wrusedw_1")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = BUS;
+ WIDTH = 7;
+ LSB_INDEX = 0;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("ph_wrusedw_1[6]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "ph_wrusedw_1";
+}
+
+SIGNAL("ph_wrusedw_1[5]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "ph_wrusedw_1";
+}
+
+SIGNAL("ph_wrusedw_1[4]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "ph_wrusedw_1";
+}
+
+SIGNAL("ph_wrusedw_1[3]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "ph_wrusedw_1";
+}
+
+SIGNAL("ph_wrusedw_1[2]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "ph_wrusedw_1";
+}
+
+SIGNAL("ph_wrusedw_1[1]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "ph_wrusedw_1";
+}
+
+SIGNAL("ph_wrusedw_1[0]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "ph_wrusedw_1";
+}
+
+SIGNAL("tx_underrun")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = BUS;
+ WIDTH = 2;
+ LSB_INDEX = 0;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("tx_underrun[1]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "tx_underrun";
+}
+
+SIGNAL("tx_underrun[0]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "tx_underrun";
+}
+
+SIGNAL("usb_pkt_rdy")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("usb_counter")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = BUS;
+ WIDTH = 9;
+ LSB_INDEX = 0;
+ DIRECTION = BURIED;
+ PARENT = "";
+}
+
+SIGNAL("usb_counter[8]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = BURIED;
+ PARENT = "usb_counter";
+}
+
+SIGNAL("usb_counter[7]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = BURIED;
+ PARENT = "usb_counter";
+}
+
+SIGNAL("usb_counter[6]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = BURIED;
+ PARENT = "usb_counter";
+}
+
+SIGNAL("usb_counter[5]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = BURIED;
+ PARENT = "usb_counter";
+}
+
+SIGNAL("usb_counter[4]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = BURIED;
+ PARENT = "usb_counter";
+}
+
+SIGNAL("usb_counter[3]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = BURIED;
+ PARENT = "usb_counter";
+}
+
+SIGNAL("usb_counter[2]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = BURIED;
+ PARENT = "usb_counter";
+}
+
+SIGNAL("usb_counter[1]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = BURIED;
+ PARENT = "usb_counter";
+}
+
+SIGNAL("usb_counter[0]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = BURIED;
+ PARENT = "usb_counter";
+}
+
+SIGNAL("dbg_sample_counter_1")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = BUS;
+ WIDTH = 8;
+ LSB_INDEX = 0;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("dbg_sample_counter_1[7]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dbg_sample_counter_1";
+}
+
+SIGNAL("dbg_sample_counter_1[6]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dbg_sample_counter_1";
+}
+
+SIGNAL("dbg_sample_counter_1[5]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dbg_sample_counter_1";
+}
+
+SIGNAL("dbg_sample_counter_1[4]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dbg_sample_counter_1";
+}
+
+SIGNAL("dbg_sample_counter_1[3]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dbg_sample_counter_1";
+}
+
+SIGNAL("dbg_sample_counter_1[2]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dbg_sample_counter_1";
+}
+
+SIGNAL("dbg_sample_counter_1[1]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dbg_sample_counter_1";
+}
+
+SIGNAL("dbg_sample_counter_1[0]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dbg_sample_counter_1";
+}
+
+TRANSITION_LIST("clk")
+{
+ NODE
+ {
+ REPEAT = 1;
+ NODE
+ {
+ REPEAT = 2500;
+ LEVEL 0 FOR 10.0;
+ LEVEL 1 FOR 10.0;
+ }
+ }
+}
+
+TRANSITION_LIST("chan_data_0[15]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("chan_data_0[14]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("chan_data_0[13]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("chan_data_0[12]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("chan_data_0[11]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("chan_data_0[10]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("chan_data_0[9]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("chan_data_0[8]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("chan_data_0[7]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("chan_data_0[6]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("chan_data_0[5]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("chan_data_0[4]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("chan_data_0[3]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("chan_data_0[2]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("chan_data_0[1]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("chan_data_0[0]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("rxstrobe")
+{
+ NODE
+ {
+ REPEAT = 1;
+ NODE
+ {
+ REPEAT = 625;
+ LEVEL 0 FOR 60.0;
+ LEVEL 1 FOR 20.0;
+ }
+ }
+}
+
+TRANSITION_LIST("reset")
+{
+ NODE
+ {
+ REPEAT = 1;
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 1 FOR 80.0;
+ LEVEL 0 FOR 49920.0;
+ }
+ }
+}
+
+TRANSITION_LIST("reset_regs")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usbclk")
+{
+ NODE
+ {
+ REPEAT = 1;
+ NODE
+ {
+ REPEAT = 2500;
+ LEVEL 0 FOR 10.0;
+ LEVEL 1 FOR 10.0;
+ }
+ }
+}
+
+TRANSITION_LIST("timestamp[31]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[30]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[29]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[28]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[27]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[26]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[25]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[24]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[23]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[22]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[21]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[20]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[19]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[18]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[17]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[16]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[15]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[14]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[13]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[12]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[11]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[10]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[9]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[8]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[7]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[6]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[5]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[4]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[3]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[2]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[1]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("timestamp[0]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("cd_full_1")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("cd_wrusedw_1[9]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("cd_wrusedw_1[8]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("cd_wrusedw_1[7]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("cd_wrusedw_1[6]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("cd_wrusedw_1[5]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("cd_wrusedw_1[4]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("cd_wrusedw_1[3]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("cd_wrusedw_1[2]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("cd_wrusedw_1[1]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("cd_wrusedw_1[0]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_chan_sel[3]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_chan_sel[2]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_chan_sel[1]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_chan_sel[0]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_iq")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_num_pkt_0[6]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_num_pkt_0[5]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_num_pkt_0[4]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_num_pkt_0[3]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_num_pkt_0[2]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_num_pkt_0[1]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_num_pkt_0[0]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_num_pkt_1[6]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_num_pkt_1[5]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_num_pkt_1[4]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_num_pkt_1[3]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_num_pkt_1[2]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_num_pkt_1[1]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_num_pkt_1[0]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_rx_wren")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_switch_ok")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("ph_full_1")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("rd_data_en_1")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("rx_WR")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("rx_WR_done")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("rx_WR_enabled")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("rx_databus[15]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("rx_databus[14]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("rx_databus[13]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("rx_databus[12]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("rx_databus[11]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("rx_databus[10]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("rx_databus[9]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("rx_databus[8]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("rx_databus[7]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("rx_databus[6]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("rx_databus[5]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("rx_databus[4]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("rx_databus[3]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("rx_databus[2]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("rx_databus[1]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("rx_databus[0]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("rx_overrun")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("save_header_1")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usb_data[15]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usb_data[14]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usb_data[13]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usb_data[12]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usb_data[11]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usb_data[10]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usb_data[9]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usb_data[8]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usb_data[7]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usb_data[6]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usb_data[5]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usb_data[4]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usb_data[3]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usb_data[2]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usb_data[1]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usb_data[0]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usb_rd")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usb_reset")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("ph_wrusedw_1[6]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("ph_wrusedw_1[5]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("ph_wrusedw_1[4]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("ph_wrusedw_1[3]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("ph_wrusedw_1[2]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("ph_wrusedw_1[1]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("ph_wrusedw_1[0]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("tx_underrun[1]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("tx_underrun[0]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usb_pkt_rdy")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usb_counter[8]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usb_counter[7]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usb_counter[6]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usb_counter[5]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usb_counter[4]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usb_counter[3]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usb_counter[2]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usb_counter[1]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("usb_counter[0]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_sample_counter_1[7]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_sample_counter_1[6]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_sample_counter_1[5]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_sample_counter_1[4]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_sample_counter_1[3]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_sample_counter_1[2]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_sample_counter_1[1]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 50000.0;
+ }
+}
+
+TRANSITION_LIST("dbg_sample_counter_1[0]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 50000.0;
+ }
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "reset";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 0;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "reset_regs";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 1;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "clk";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 2;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "rxstrobe";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 3;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_iq";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 4;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_rx_wren";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 5;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 6;
+ TREE_LEVEL = 0;
+ CHILDREN = 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,
23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[31]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 7;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[30]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 8;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[29]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 9;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[28]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 10;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[27]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 11;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[26]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 12;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[25]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 13;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[24]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 14;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[23]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 15;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[22]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 16;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[21]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 17;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[20]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 18;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[19]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 19;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[18]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 20;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[17]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 21;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[16]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 22;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[15]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 23;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[14]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 24;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[13]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 25;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[12]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 26;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[11]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 27;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[10]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 28;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[9]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 29;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[8]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 30;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[7]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 31;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[6]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 32;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[5]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 33;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[4]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 34;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[3]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 35;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[2]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 36;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[1]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 37;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "timestamp[0]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 38;
+ TREE_LEVEL = 1;
+ PARENT = 6;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "chan_data_0";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 39;
+ TREE_LEVEL = 0;
+ CHILDREN = 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54,
55;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "chan_data_0[15]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 40;
+ TREE_LEVEL = 1;
+ PARENT = 39;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "chan_data_0[14]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 41;
+ TREE_LEVEL = 1;
+ PARENT = 39;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "chan_data_0[13]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 42;
+ TREE_LEVEL = 1;
+ PARENT = 39;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "chan_data_0[12]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 43;
+ TREE_LEVEL = 1;
+ PARENT = 39;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "chan_data_0[11]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 44;
+ TREE_LEVEL = 1;
+ PARENT = 39;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "chan_data_0[10]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 45;
+ TREE_LEVEL = 1;
+ PARENT = 39;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "chan_data_0[9]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 46;
+ TREE_LEVEL = 1;
+ PARENT = 39;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "chan_data_0[8]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 47;
+ TREE_LEVEL = 1;
+ PARENT = 39;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "chan_data_0[7]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 48;
+ TREE_LEVEL = 1;
+ PARENT = 39;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "chan_data_0[6]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 49;
+ TREE_LEVEL = 1;
+ PARENT = 39;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "chan_data_0[5]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 50;
+ TREE_LEVEL = 1;
+ PARENT = 39;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "chan_data_0[4]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 51;
+ TREE_LEVEL = 1;
+ PARENT = 39;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "chan_data_0[3]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 52;
+ TREE_LEVEL = 1;
+ PARENT = 39;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "chan_data_0[2]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 53;
+ TREE_LEVEL = 1;
+ PARENT = 39;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "chan_data_0[1]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 54;
+ TREE_LEVEL = 1;
+ PARENT = 39;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "chan_data_0[0]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 55;
+ TREE_LEVEL = 1;
+ PARENT = 39;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_sample_counter_1";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 56;
+ TREE_LEVEL = 0;
+ CHILDREN = 57, 58, 59, 60, 61, 62, 63, 64;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_sample_counter_1[7]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 57;
+ TREE_LEVEL = 1;
+ PARENT = 56;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_sample_counter_1[6]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 58;
+ TREE_LEVEL = 1;
+ PARENT = 56;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_sample_counter_1[5]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 59;
+ TREE_LEVEL = 1;
+ PARENT = 56;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_sample_counter_1[4]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 60;
+ TREE_LEVEL = 1;
+ PARENT = 56;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_sample_counter_1[3]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 61;
+ TREE_LEVEL = 1;
+ PARENT = 56;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_sample_counter_1[2]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 62;
+ TREE_LEVEL = 1;
+ PARENT = 56;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_sample_counter_1[1]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 63;
+ TREE_LEVEL = 1;
+ PARENT = 56;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_sample_counter_1[0]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 64;
+ TREE_LEVEL = 1;
+ PARENT = 56;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "save_header_1";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 65;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "ph_full_1";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 66;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "cd_full_1";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 67;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "rd_data_en_1";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 68;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_num_pkt_0";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 69;
+ TREE_LEVEL = 0;
+ CHILDREN = 70, 71, 72, 73, 74, 75, 76;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_num_pkt_0[6]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 70;
+ TREE_LEVEL = 1;
+ PARENT = 69;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_num_pkt_0[5]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 71;
+ TREE_LEVEL = 1;
+ PARENT = 69;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_num_pkt_0[4]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 72;
+ TREE_LEVEL = 1;
+ PARENT = 69;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_num_pkt_0[3]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 73;
+ TREE_LEVEL = 1;
+ PARENT = 69;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_num_pkt_0[2]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 74;
+ TREE_LEVEL = 1;
+ PARENT = 69;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_num_pkt_0[1]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 75;
+ TREE_LEVEL = 1;
+ PARENT = 69;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_num_pkt_0[0]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 76;
+ TREE_LEVEL = 1;
+ PARENT = 69;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "ph_wrusedw_1";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 77;
+ TREE_LEVEL = 0;
+ CHILDREN = 78, 79, 80, 81, 82, 83, 84;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "ph_wrusedw_1[6]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 78;
+ TREE_LEVEL = 1;
+ PARENT = 77;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "ph_wrusedw_1[5]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 79;
+ TREE_LEVEL = 1;
+ PARENT = 77;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "ph_wrusedw_1[4]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 80;
+ TREE_LEVEL = 1;
+ PARENT = 77;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "ph_wrusedw_1[3]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 81;
+ TREE_LEVEL = 1;
+ PARENT = 77;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "ph_wrusedw_1[2]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 82;
+ TREE_LEVEL = 1;
+ PARENT = 77;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "ph_wrusedw_1[1]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 83;
+ TREE_LEVEL = 1;
+ PARENT = 77;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "ph_wrusedw_1[0]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 84;
+ TREE_LEVEL = 1;
+ PARENT = 77;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "cd_wrusedw_1";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 85;
+ TREE_LEVEL = 0;
+ CHILDREN = 86, 87, 88, 89, 90, 91, 92, 93, 94, 95;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "cd_wrusedw_1[9]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 86;
+ TREE_LEVEL = 1;
+ PARENT = 85;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "cd_wrusedw_1[8]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 87;
+ TREE_LEVEL = 1;
+ PARENT = 85;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "cd_wrusedw_1[7]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 88;
+ TREE_LEVEL = 1;
+ PARENT = 85;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "cd_wrusedw_1[6]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 89;
+ TREE_LEVEL = 1;
+ PARENT = 85;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "cd_wrusedw_1[5]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 90;
+ TREE_LEVEL = 1;
+ PARENT = 85;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "cd_wrusedw_1[4]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 91;
+ TREE_LEVEL = 1;
+ PARENT = 85;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "cd_wrusedw_1[3]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 92;
+ TREE_LEVEL = 1;
+ PARENT = 85;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "cd_wrusedw_1[2]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 93;
+ TREE_LEVEL = 1;
+ PARENT = 85;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "cd_wrusedw_1[1]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 94;
+ TREE_LEVEL = 1;
+ PARENT = 85;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "cd_wrusedw_1[0]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 95;
+ TREE_LEVEL = 1;
+ PARENT = 85;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_num_pkt_1";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 96;
+ TREE_LEVEL = 0;
+ CHILDREN = 97, 98, 99, 100, 101, 102, 103;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_num_pkt_1[6]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 97;
+ TREE_LEVEL = 1;
+ PARENT = 96;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_num_pkt_1[5]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 98;
+ TREE_LEVEL = 1;
+ PARENT = 96;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_num_pkt_1[4]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 99;
+ TREE_LEVEL = 1;
+ PARENT = 96;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_num_pkt_1[3]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 100;
+ TREE_LEVEL = 1;
+ PARENT = 96;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_num_pkt_1[2]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 101;
+ TREE_LEVEL = 1;
+ PARENT = 96;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_num_pkt_1[1]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 102;
+ TREE_LEVEL = 1;
+ PARENT = 96;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_num_pkt_1[0]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 103;
+ TREE_LEVEL = 1;
+ PARENT = 96;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "rx_WR";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 104;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "rx_WR_done";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 105;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "rx_WR_enabled";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 106;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "rx_databus";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 107;
+ TREE_LEVEL = 0;
+ CHILDREN = 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119,
120, 121, 122, 123;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "rx_databus[15]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 108;
+ TREE_LEVEL = 1;
+ PARENT = 107;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "rx_databus[14]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 109;
+ TREE_LEVEL = 1;
+ PARENT = 107;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "rx_databus[13]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 110;
+ TREE_LEVEL = 1;
+ PARENT = 107;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "rx_databus[12]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 111;
+ TREE_LEVEL = 1;
+ PARENT = 107;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "rx_databus[11]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 112;
+ TREE_LEVEL = 1;
+ PARENT = 107;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "rx_databus[10]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 113;
+ TREE_LEVEL = 1;
+ PARENT = 107;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "rx_databus[9]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 114;
+ TREE_LEVEL = 1;
+ PARENT = 107;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "rx_databus[8]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 115;
+ TREE_LEVEL = 1;
+ PARENT = 107;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "rx_databus[7]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 116;
+ TREE_LEVEL = 1;
+ PARENT = 107;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "rx_databus[6]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 117;
+ TREE_LEVEL = 1;
+ PARENT = 107;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "rx_databus[5]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 118;
+ TREE_LEVEL = 1;
+ PARENT = 107;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "rx_databus[4]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 119;
+ TREE_LEVEL = 1;
+ PARENT = 107;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "rx_databus[3]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 120;
+ TREE_LEVEL = 1;
+ PARENT = 107;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "rx_databus[2]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 121;
+ TREE_LEVEL = 1;
+ PARENT = 107;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "rx_databus[1]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 122;
+ TREE_LEVEL = 1;
+ PARENT = 107;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "rx_databus[0]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 123;
+ TREE_LEVEL = 1;
+ PARENT = 107;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_switch_ok";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 124;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_chan_sel";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 125;
+ TREE_LEVEL = 0;
+ CHILDREN = 126, 127, 128, 129;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_chan_sel[3]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 126;
+ TREE_LEVEL = 1;
+ PARENT = 125;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_chan_sel[2]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 127;
+ TREE_LEVEL = 1;
+ PARENT = 125;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_chan_sel[1]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 128;
+ TREE_LEVEL = 1;
+ PARENT = 125;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dbg_chan_sel[0]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 129;
+ TREE_LEVEL = 1;
+ PARENT = 125;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_pkt_rdy";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 130;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_reset";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 131;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_rd";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 132;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usbclk";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 133;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_data";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 134;
+ TREE_LEVEL = 0;
+ CHILDREN = 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146,
147, 148, 149, 150;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_data[15]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 135;
+ TREE_LEVEL = 1;
+ PARENT = 134;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_data[14]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 136;
+ TREE_LEVEL = 1;
+ PARENT = 134;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_data[13]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 137;
+ TREE_LEVEL = 1;
+ PARENT = 134;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_data[12]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 138;
+ TREE_LEVEL = 1;
+ PARENT = 134;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_data[11]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 139;
+ TREE_LEVEL = 1;
+ PARENT = 134;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_data[10]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 140;
+ TREE_LEVEL = 1;
+ PARENT = 134;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_data[9]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 141;
+ TREE_LEVEL = 1;
+ PARENT = 134;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_data[8]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 142;
+ TREE_LEVEL = 1;
+ PARENT = 134;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_data[7]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 143;
+ TREE_LEVEL = 1;
+ PARENT = 134;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_data[6]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 144;
+ TREE_LEVEL = 1;
+ PARENT = 134;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_data[5]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 145;
+ TREE_LEVEL = 1;
+ PARENT = 134;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_data[4]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 146;
+ TREE_LEVEL = 1;
+ PARENT = 134;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_data[3]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 147;
+ TREE_LEVEL = 1;
+ PARENT = 134;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_data[2]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 148;
+ TREE_LEVEL = 1;
+ PARENT = 134;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_data[1]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 149;
+ TREE_LEVEL = 1;
+ PARENT = 134;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_data[0]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 150;
+ TREE_LEVEL = 1;
+ PARENT = 134;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_counter";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 151;
+ TREE_LEVEL = 0;
+ CHILDREN = 152, 153, 154, 155, 156, 157, 158, 159, 160;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_counter[8]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 152;
+ TREE_LEVEL = 1;
+ PARENT = 151;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_counter[7]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 153;
+ TREE_LEVEL = 1;
+ PARENT = 151;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_counter[6]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 154;
+ TREE_LEVEL = 1;
+ PARENT = 151;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_counter[5]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 155;
+ TREE_LEVEL = 1;
+ PARENT = 151;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_counter[4]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 156;
+ TREE_LEVEL = 1;
+ PARENT = 151;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_counter[3]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 157;
+ TREE_LEVEL = 1;
+ PARENT = 151;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_counter[2]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 158;
+ TREE_LEVEL = 1;
+ PARENT = 151;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_counter[1]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 159;
+ TREE_LEVEL = 1;
+ PARENT = 151;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usb_counter[0]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 160;
+ TREE_LEVEL = 1;
+ PARENT = 151;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "rx_overrun";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 161;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "tx_underrun";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 162;
+ TREE_LEVEL = 0;
+ CHILDREN = 163, 164;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "tx_underrun[1]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 163;
+ TREE_LEVEL = 1;
+ PARENT = 162;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "tx_underrun[0]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Hexadecimal;
+ TREE_INDEX = 164;
+ TREE_LEVEL = 1;
+ PARENT = 162;
+}
+
+TIME_BAR
+{
+ TIME = 0;
+ MASTER = TRUE;
+}
+;
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.bsf
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.bsf
(rev 0)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.bsf
2008-09-07 08:20:22 UTC (rev 9516)
@@ -0,0 +1,131 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 0 0 160 200)
+ (text "fifo_128x64_dc_la" (rect 29 1 150 17)(font "Arial" (font_size
10)))
+ (text "inst" (rect 8 184 25 196)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "data[63..0]" (rect 0 0 60 14)(font "Arial" (font_size
8)))
+ (text "data[63..0]" (rect 20 26 71 39)(font "Arial" (font_size
8)))
+ (line (pt 0 32)(pt 16 32)(line_width 3))
+ )
+ (port
+ (pt 0 56)
+ (input)
+ (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+ (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
+ (line (pt 0 56)(pt 16 56)(line_width 1))
+ )
+ (port
+ (pt 0 72)
+ (input)
+ (text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+ (text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8)))
+ (line (pt 0 72)(pt 16 72)(line_width 1))
+ )
+ (port
+ (pt 0 104)
+ (input)
+ (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
+ (text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8)))
+ (line (pt 0 104)(pt 16 104)(line_width 1))
+ )
+ (port
+ (pt 0 120)
+ (input)
+ (text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8)))
+ (text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8)))
+ (line (pt 0 120)(pt 16 120)(line_width 1))
+ )
+ (port
+ (pt 0 176)
+ (input)
+ (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
+ (text "aclr" (rect 20 170 37 183)(font "Arial" (font_size 8)))
+ (line (pt 0 176)(pt 16 176)(line_width 1))
+ )
+ (port
+ (pt 160 40)
+ (output)
+ (text "wrfull" (rect 0 0 33 14)(font "Arial" (font_size 8)))
+ (text "wrfull" (rect 113 34 138 47)(font "Arial" (font_size 8)))
+ (line (pt 160 40)(pt 144 40)(line_width 1))
+ )
+ (port
+ (pt 160 56)
+ (output)
+ (text "wrempty" (rect 0 0 50 14)(font "Arial" (font_size 8)))
+ (text "wrempty" (rect 98 50 137 63)(font "Arial" (font_size 8)))
+ (line (pt 160 56)(pt 144 56)(line_width 1))
+ )
+ (port
+ (pt 160 72)
+ (output)
+ (text "wrusedw[6..0]" (rect 0 0 84 14)(font "Arial" (font_size
8)))
+ (text "wrusedw[6..0]" (rect 69 66 132 79)(font "Arial"
(font_size 8)))
+ (line (pt 160 72)(pt 144 72)(line_width 3))
+ )
+ (port
+ (pt 160 96)
+ (output)
+ (text "q[63..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+ (text "q[63..0]" (rect 105 90 141 103)(font "Arial" (font_size
8)))
+ (line (pt 160 96)(pt 144 96)(line_width 3))
+ )
+ (port
+ (pt 160 120)
+ (output)
+ (text "rdfull" (rect 0 0 28 14)(font "Arial" (font_size 8)))
+ (text "rdfull" (rect 117 114 141 127)(font "Arial" (font_size
8)))
+ (line (pt 160 120)(pt 144 120)(line_width 1))
+ )
+ (port
+ (pt 160 136)
+ (output)
+ (text "rdempty" (rect 0 0 46 14)(font "Arial" (font_size 8)))
+ (text "rdempty" (rect 102 130 140 143)(font "Arial" (font_size
8)))
+ (line (pt 160 136)(pt 144 136)(line_width 1))
+ )
+ (port
+ (pt 160 152)
+ (output)
+ (text "rdusedw[6..0]" (rect 0 0 80 14)(font "Arial" (font_size
8)))
+ (text "rdusedw[6..0]" (rect 73 146 135 159)(font "Arial"
(font_size 8)))
+ (line (pt 160 152)(pt 144 152)(line_width 3))
+ )
+ (drawing
+ (text "(ack)" (rect 51 99 72 111)(font "Arial" ))
+ (text "64 bits x 128 words" (rect 63 172 144 184)(font "Arial"
))
+ (line (pt 16 16)(pt 144 16)(line_width 1))
+ (line (pt 144 16)(pt 144 184)(line_width 1))
+ (line (pt 144 184)(pt 16 184)(line_width 1))
+ (line (pt 16 184)(pt 16 16)(line_width 1))
+ (line (pt 16 84)(pt 144 84)(line_width 1))
+ (line (pt 16 164)(pt 144 164)(line_width 1))
+ (line (pt 16 66)(pt 22 72)(line_width 1))
+ (line (pt 22 72)(pt 16 78)(line_width 1))
+ (line (pt 16 114)(pt 22 120)(line_width 1))
+ (line (pt 22 120)(pt 16 126)(line_width 1))
+ )
+)
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.cmp
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.cmp
(rev 0)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.cmp
2008-09-07 08:20:22 UTC (rev 9516)
@@ -0,0 +1,33 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files from any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+component fifo_128x64_dc_la
+ PORT
+ (
+ aclr : IN STD_LOGIC := '0';
+ data : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ rdreq : IN STD_LOGIC ;
+ wrclk : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
+ rdempty : OUT STD_LOGIC ;
+ rdfull : OUT STD_LOGIC ;
+ rdusedw : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
+ wrempty : OUT STD_LOGIC ;
+ wrfull : OUT STD_LOGIC ;
+ wrusedw : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
+ );
+end component;
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.inc
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.inc
(rev 0)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.inc
2008-09-07 08:20:22 UTC (rev 9516)
@@ -0,0 +1,34 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files from any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+FUNCTION fifo_128x64_dc_la
+(
+ aclr,
+ data[63..0],
+ rdclk,
+ rdreq,
+ wrclk,
+ wrreq
+)
+
+RETURNS (
+ q[63..0],
+ rdempty,
+ rdfull,
+ rdusedw[6..0],
+ wrempty,
+ wrfull,
+ wrusedw[6..0]
+);
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.qip
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.qip
(rev 0)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.qip
2008-09-07 08:20:22 UTC (rev 9516)
@@ -0,0 +1,8 @@
+set_global_assignment -name IP_TOOL_NAME "FIFO"
+set_global_assignment -name IP_TOOL_VERSION "8.0"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path)
"fifo_128x64_dc_la.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path)
"fifo_128x64_dc_la.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path)
"fifo_128x64_dc_la_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path)
"fifo_128x64_dc_la_bb.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path)
"fifo_128x64_dc_la.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path)
"fifo_128x64_dc_la.cmp"]
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.v
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.v
(rev 0)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.v
2008-09-07 08:20:22 UTC (rev 9516)
@@ -0,0 +1,194 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo
+
+// ============================================================
+// File Name: fifo_128x64_dc_la.v
+// Megafunction Name(s):
+// dcfifo
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 8.0 Build 231 07/10/2008 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2008 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module fifo_128x64_dc_la (
+ aclr,
+ data,
+ rdclk,
+ rdreq,
+ wrclk,
+ wrreq,
+ q,
+ rdempty,
+ rdfull,
+ rdusedw,
+ wrempty,
+ wrfull,
+ wrusedw);
+
+ input aclr;
+ input [63:0] data;
+ input rdclk;
+ input rdreq;
+ input wrclk;
+ input wrreq;
+ output [63:0] q;
+ output rdempty;
+ output rdfull;
+ output [6:0] rdusedw;
+ output wrempty;
+ output wrfull;
+ output [6:0] wrusedw;
+
+ wire sub_wire0;
+ wire sub_wire1;
+ wire [6:0] sub_wire2;
+ wire sub_wire3;
+ wire sub_wire4;
+ wire [63:0] sub_wire5;
+ wire [6:0] sub_wire6;
+ wire rdfull = sub_wire0;
+ wire rdempty = sub_wire1;
+ wire [6:0] wrusedw = sub_wire2[6:0];
+ wire wrfull = sub_wire3;
+ wire wrempty = sub_wire4;
+ wire [63:0] q = sub_wire5[63:0];
+ wire [6:0] rdusedw = sub_wire6[6:0];
+
+ dcfifo dcfifo_component (
+ .wrclk (wrclk),
+ .rdreq (rdreq),
+ .aclr (aclr),
+ .rdclk (rdclk),
+ .wrreq (wrreq),
+ .data (data),
+ .rdfull (sub_wire0),
+ .rdempty (sub_wire1),
+ .wrusedw (sub_wire2),
+ .wrfull (sub_wire3),
+ .wrempty (sub_wire4),
+ .q (sub_wire5),
+ .rdusedw (sub_wire6));
+ defparam
+ dcfifo_component.add_ram_output_register = "OFF",
+ dcfifo_component.clocks_are_synchronized = "FALSE",
+ dcfifo_component.intended_device_family = "Cyclone",
+ dcfifo_component.lpm_numwords = 128,
+ dcfifo_component.lpm_showahead = "ON",
+ dcfifo_component.lpm_type = "dcfifo",
+ dcfifo_component.lpm_width = 64,
+ dcfifo_component.lpm_widthu = 7,
+ dcfifo_component.overflow_checking = "ON",
+ dcfifo_component.underflow_checking = "ON",
+ dcfifo_component.use_eab = "ON";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "128"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "64"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "64"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "1"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL data[63..0]
+// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL q[63..0]
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL rdfull
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: rdusedw 0 0 7 0 OUTPUT NODEFVAL rdusedw[6..0]
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL wrempty
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: USED_PORT: wrusedw 0 0 7 0 OUTPUT NODEFVAL wrusedw[6..0]
+// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
+// Retrieval info: CONNECT: q 0 0 64 0 @q 0 0 64 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 7 0 @rdusedw 0 0 7 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 7 0 @wrusedw 0 0 7 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x64_dc_la.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x64_dc_la.inc TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x64_dc_la.cmp TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x64_dc_la.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x64_dc_la_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x64_dc_la_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x64_dc_la_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x64_dc_la_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la_bb.v
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la_bb.v
(rev 0)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la_bb.v
2008-09-07 08:20:22 UTC (rev 9516)
@@ -0,0 +1,146 @@
+// megafunction wizard: %FIFO%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo
+
+// ============================================================
+// File Name: fifo_128x64_dc_la.v
+// Megafunction Name(s):
+// dcfifo
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 8.0 Build 231 07/10/2008 SP 1 SJ Web Edition
+// ************************************************************
+
+//Copyright (C) 1991-2008 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+module fifo_128x64_dc_la (
+ aclr,
+ data,
+ rdclk,
+ rdreq,
+ wrclk,
+ wrreq,
+ q,
+ rdempty,
+ rdfull,
+ rdusedw,
+ wrempty,
+ wrfull,
+ wrusedw);
+
+ input aclr;
+ input [63:0] data;
+ input rdclk;
+ input rdreq;
+ input wrclk;
+ input wrreq;
+ output [63:0] q;
+ output rdempty;
+ output rdfull;
+ output [6:0] rdusedw;
+ output wrempty;
+ output wrfull;
+ output [6:0] wrusedw;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "128"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "64"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "64"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "1"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL data[63..0]
+// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL q[63..0]
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL rdfull
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: rdusedw 0 0 7 0 OUTPUT NODEFVAL rdusedw[6..0]
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL wrempty
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: USED_PORT: wrusedw 0 0 7 0 OUTPUT NODEFVAL wrusedw[6..0]
+// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
+// Retrieval info: CONNECT: q 0 0 64 0 @q 0 0 64 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 7 0 @rdusedw 0 0 7 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 7 0 @wrusedw 0 0 7 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x64_dc_la.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x64_dc_la.inc TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x64_dc_la.cmp TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x64_dc_la.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x64_dc_la_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x64_dc_la_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x64_dc_la_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x64_dc_la_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la_inst.v
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la_inst.v
(rev 0)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la_inst.v
2008-09-07 08:20:22 UTC (rev 9516)
@@ -0,0 +1,15 @@
+fifo_128x64_dc_la fifo_128x64_dc_la_inst (
+ .aclr ( aclr_sig ),
+ .data ( data_sig ),
+ .rdclk ( rdclk_sig ),
+ .rdreq ( rdreq_sig ),
+ .wrclk ( wrclk_sig ),
+ .wrreq ( wrreq_sig ),
+ .q ( q_sig ),
+ .rdempty ( rdempty_sig ),
+ .rdfull ( rdfull_sig ),
+ .rdusedw ( rdusedw_sig ),
+ .wrempty ( wrempty_sig ),
+ .wrfull ( wrfull_sig ),
+ .wrusedw ( wrusedw_sig )
+ );
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.bsf
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.bsf
(rev 0)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.bsf
2008-09-07 08:20:22 UTC (rev 9516)
@@ -0,0 +1,131 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 0 0 160 200)
+ (text "fifo_1kx16_dc_la" (rect 32 1 145 17)(font "Arial" (font_size
10)))
+ (text "inst" (rect 8 184 25 196)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size
8)))
+ (text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size
8)))
+ (line (pt 0 32)(pt 16 32)(line_width 3))
+ )
+ (port
+ (pt 0 56)
+ (input)
+ (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+ (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
+ (line (pt 0 56)(pt 16 56)(line_width 1))
+ )
+ (port
+ (pt 0 72)
+ (input)
+ (text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+ (text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8)))
+ (line (pt 0 72)(pt 16 72)(line_width 1))
+ )
+ (port
+ (pt 0 104)
+ (input)
+ (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
+ (text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8)))
+ (line (pt 0 104)(pt 16 104)(line_width 1))
+ )
+ (port
+ (pt 0 120)
+ (input)
+ (text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8)))
+ (text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8)))
+ (line (pt 0 120)(pt 16 120)(line_width 1))
+ )
+ (port
+ (pt 0 176)
+ (input)
+ (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
+ (text "aclr" (rect 20 170 37 183)(font "Arial" (font_size 8)))
+ (line (pt 0 176)(pt 16 176)(line_width 1))
+ )
+ (port
+ (pt 160 40)
+ (output)
+ (text "wrfull" (rect 0 0 33 14)(font "Arial" (font_size 8)))
+ (text "wrfull" (rect 113 34 138 47)(font "Arial" (font_size 8)))
+ (line (pt 160 40)(pt 144 40)(line_width 1))
+ )
+ (port
+ (pt 160 56)
+ (output)
+ (text "wrempty" (rect 0 0 50 14)(font "Arial" (font_size 8)))
+ (text "wrempty" (rect 98 50 137 63)(font "Arial" (font_size 8)))
+ (line (pt 160 56)(pt 144 56)(line_width 1))
+ )
+ (port
+ (pt 160 72)
+ (output)
+ (text "wrusedw[9..0]" (rect 0 0 84 14)(font "Arial" (font_size
8)))
+ (text "wrusedw[9..0]" (rect 69 66 132 79)(font "Arial"
(font_size 8)))
+ (line (pt 160 72)(pt 144 72)(line_width 3))
+ )
+ (port
+ (pt 160 96)
+ (output)
+ (text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+ (text "q[15..0]" (rect 105 90 141 103)(font "Arial" (font_size
8)))
+ (line (pt 160 96)(pt 144 96)(line_width 3))
+ )
+ (port
+ (pt 160 120)
+ (output)
+ (text "rdfull" (rect 0 0 28 14)(font "Arial" (font_size 8)))
+ (text "rdfull" (rect 117 114 141 127)(font "Arial" (font_size
8)))
+ (line (pt 160 120)(pt 144 120)(line_width 1))
+ )
+ (port
+ (pt 160 136)
+ (output)
+ (text "rdempty" (rect 0 0 46 14)(font "Arial" (font_size 8)))
+ (text "rdempty" (rect 102 130 140 143)(font "Arial" (font_size
8)))
+ (line (pt 160 136)(pt 144 136)(line_width 1))
+ )
+ (port
+ (pt 160 152)
+ (output)
+ (text "rdusedw[9..0]" (rect 0 0 80 14)(font "Arial" (font_size
8)))
+ (text "rdusedw[9..0]" (rect 73 146 135 159)(font "Arial"
(font_size 8)))
+ (line (pt 160 152)(pt 144 152)(line_width 3))
+ )
+ (drawing
+ (text "(ack)" (rect 51 99 72 111)(font "Arial" ))
+ (text "16 bits x 1024 words" (rect 58 172 144 184)(font "Arial"
))
+ (line (pt 16 16)(pt 144 16)(line_width 1))
+ (line (pt 144 16)(pt 144 184)(line_width 1))
+ (line (pt 144 184)(pt 16 184)(line_width 1))
+ (line (pt 16 184)(pt 16 16)(line_width 1))
+ (line (pt 16 84)(pt 144 84)(line_width 1))
+ (line (pt 16 164)(pt 144 164)(line_width 1))
+ (line (pt 16 66)(pt 22 72)(line_width 1))
+ (line (pt 22 72)(pt 16 78)(line_width 1))
+ (line (pt 16 114)(pt 22 120)(line_width 1))
+ (line (pt 22 120)(pt 16 126)(line_width 1))
+ )
+)
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.cmp
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.cmp
(rev 0)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.cmp
2008-09-07 08:20:22 UTC (rev 9516)
@@ -0,0 +1,33 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files from any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+component fifo_1kx16_dc_la
+ PORT
+ (
+ aclr : IN STD_LOGIC := '0';
+ data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ rdreq : IN STD_LOGIC ;
+ wrclk : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
+ rdempty : OUT STD_LOGIC ;
+ rdfull : OUT STD_LOGIC ;
+ rdusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
+ wrempty : OUT STD_LOGIC ;
+ wrfull : OUT STD_LOGIC ;
+ wrusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
+ );
+end component;
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.inc
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.inc
(rev 0)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.inc
2008-09-07 08:20:22 UTC (rev 9516)
@@ -0,0 +1,34 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files from any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+FUNCTION fifo_1kx16_dc_la
+(
+ aclr,
+ data[15..0],
+ rdclk,
+ rdreq,
+ wrclk,
+ wrreq
+)
+
+RETURNS (
+ q[15..0],
+ rdempty,
+ rdfull,
+ rdusedw[9..0],
+ wrempty,
+ wrfull,
+ wrusedw[9..0]
+);
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.qip
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.qip
(rev 0)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.qip
2008-09-07 08:20:22 UTC (rev 9516)
@@ -0,0 +1,8 @@
+set_global_assignment -name IP_TOOL_NAME "FIFO"
+set_global_assignment -name IP_TOOL_VERSION "8.0"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path)
"fifo_1kx16_dc_la.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path)
"fifo_1kx16_dc_la.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path)
"fifo_1kx16_dc_la_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path)
"fifo_1kx16_dc_la_bb.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path)
"fifo_1kx16_dc_la.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path)
"fifo_1kx16_dc_la.cmp"]
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.v
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.v
(rev 0)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.v
2008-09-07 08:20:22 UTC (rev 9516)
@@ -0,0 +1,194 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo
+
+// ============================================================
+// File Name: fifo_1kx16_dc_la.v
+// Megafunction Name(s):
+// dcfifo
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 8.0 Build 231 07/10/2008 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2008 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module fifo_1kx16_dc_la (
+ aclr,
+ data,
+ rdclk,
+ rdreq,
+ wrclk,
+ wrreq,
+ q,
+ rdempty,
+ rdfull,
+ rdusedw,
+ wrempty,
+ wrfull,
+ wrusedw);
+
+ input aclr;
+ input [15:0] data;
+ input rdclk;
+ input rdreq;
+ input wrclk;
+ input wrreq;
+ output [15:0] q;
+ output rdempty;
+ output rdfull;
+ output [9:0] rdusedw;
+ output wrempty;
+ output wrfull;
+ output [9:0] wrusedw;
+
+ wire sub_wire0;
+ wire sub_wire1;
+ wire [9:0] sub_wire2;
+ wire sub_wire3;
+ wire sub_wire4;
+ wire [15:0] sub_wire5;
+ wire [9:0] sub_wire6;
+ wire rdfull = sub_wire0;
+ wire rdempty = sub_wire1;
+ wire [9:0] wrusedw = sub_wire2[9:0];
+ wire wrfull = sub_wire3;
+ wire wrempty = sub_wire4;
+ wire [15:0] q = sub_wire5[15:0];
+ wire [9:0] rdusedw = sub_wire6[9:0];
+
+ dcfifo dcfifo_component (
+ .wrclk (wrclk),
+ .rdreq (rdreq),
+ .aclr (aclr),
+ .rdclk (rdclk),
+ .wrreq (wrreq),
+ .data (data),
+ .rdfull (sub_wire0),
+ .rdempty (sub_wire1),
+ .wrusedw (sub_wire2),
+ .wrfull (sub_wire3),
+ .wrempty (sub_wire4),
+ .q (sub_wire5),
+ .rdusedw (sub_wire6));
+ defparam
+ dcfifo_component.add_ram_output_register = "OFF",
+ dcfifo_component.clocks_are_synchronized = "FALSE",
+ dcfifo_component.intended_device_family = "Cyclone",
+ dcfifo_component.lpm_numwords = 1024,
+ dcfifo_component.lpm_showahead = "ON",
+ dcfifo_component.lpm_type = "dcfifo",
+ dcfifo_component.lpm_width = 16,
+ dcfifo_component.lpm_widthu = 10,
+ dcfifo_component.overflow_checking = "ON",
+ dcfifo_component.underflow_checking = "ON",
+ dcfifo_component.use_eab = "ON";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "1024"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "16"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "1"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL rdfull
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: rdusedw 0 0 10 0 OUTPUT NODEFVAL rdusedw[9..0]
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL wrempty
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL wrusedw[9..0]
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 10 0 @rdusedw 0 0 10 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_dc_la.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_dc_la.inc TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_dc_la.cmp TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_dc_la.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_dc_la_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_dc_la_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_dc_la_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_dc_la_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la_bb.v
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la_bb.v
(rev 0)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la_bb.v
2008-09-07 08:20:22 UTC (rev 9516)
@@ -0,0 +1,146 @@
+// megafunction wizard: %FIFO%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo
+
+// ============================================================
+// File Name: fifo_1kx16_dc_la.v
+// Megafunction Name(s):
+// dcfifo
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 8.0 Build 231 07/10/2008 SP 1 SJ Web Edition
+// ************************************************************
+
+//Copyright (C) 1991-2008 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+module fifo_1kx16_dc_la (
+ aclr,
+ data,
+ rdclk,
+ rdreq,
+ wrclk,
+ wrreq,
+ q,
+ rdempty,
+ rdfull,
+ rdusedw,
+ wrempty,
+ wrfull,
+ wrusedw);
+
+ input aclr;
+ input [15:0] data;
+ input rdclk;
+ input rdreq;
+ input wrclk;
+ input wrreq;
+ output [15:0] q;
+ output rdempty;
+ output rdfull;
+ output [9:0] rdusedw;
+ output wrempty;
+ output wrfull;
+ output [9:0] wrusedw;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "1024"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "16"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "1"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL rdfull
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: rdusedw 0 0 10 0 OUTPUT NODEFVAL rdusedw[9..0]
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL wrempty
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL wrusedw[9..0]
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 10 0 @rdusedw 0 0 10 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_dc_la.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_dc_la.inc TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_dc_la.cmp TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_dc_la.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_dc_la_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_dc_la_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_dc_la_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_dc_la_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la_inst.v
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la_inst.v
(rev 0)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la_inst.v
2008-09-07 08:20:22 UTC (rev 9516)
@@ -0,0 +1,15 @@
+fifo_1kx16_dc_la fifo_1kx16_dc_la_inst (
+ .aclr ( aclr_sig ),
+ .data ( data_sig ),
+ .rdclk ( rdclk_sig ),
+ .rdreq ( rdreq_sig ),
+ .wrclk ( wrclk_sig ),
+ .wrreq ( wrreq_sig ),
+ .q ( q_sig ),
+ .rdempty ( rdempty_sig ),
+ .rdfull ( rdfull_sig ),
+ .rdusedw ( rdusedw_sig ),
+ .wrempty ( wrempty_sig ),
+ .wrfull ( wrfull_sig ),
+ .wrusedw ( wrusedw_sig )
+ );
Modified:
gnuradio/branches/developers/ets/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
2008-09-07 06:36:29 UTC (rev 9515)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
2008-09-07 08:20:22 UTC (rev 9516)
@@ -27,7 +27,7 @@
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13,
2003"
-set_global_assignment -name LAST_QUARTUS_VERSION "7.2 SP2"
+set_global_assignment -name LAST_QUARTUS_VERSION "8.0 SP1"
# Pin & Location Assignments
# ==========================
@@ -265,7 +265,6 @@
# Simulator Assignments
# =====================
set_global_assignment -name START_TIME "0 ns"
-set_global_assignment -name GLITCH_INTERVAL "1 ns"
# Design Assistant Assignments
# ============================
@@ -369,9 +368,17 @@
# --------------------
-set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition
-to | -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to |
-section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ps"
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD OFF
+set_global_assignment -name VERILOG_FILE ../../inband_lib/inband_packet_defs.v
+set_global_assignment -name VERILOG_FILE ../../megacells/fifo_128x64_dc_la.v
+set_global_assignment -name VERILOG_FILE ../../megacells/fifo_1kx16_dc_la.v
+set_global_assignment -name VERILOG_FILE ../../inband_lib/rx_channel_buffer.v
set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4kx16_dc.v
set_global_assignment -name VERILOG_FILE ../../megacells/fifo_1kx16.v
set_global_assignment -name VERILOG_FILE ../../inband_lib/channel_demux.v
@@ -419,5 +426,7 @@
set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v
set_global_assignment -name VERILOG_FILE ../../inband_lib/channel_ram.v
set_global_assignment -name VERILOG_FILE ../../inband_lib/register_io.v
-set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
\ No newline at end of file
+set_global_assignment -name VERILOG_FILE ../../inband_lib/usb_packet_builder.v
+
+set_global_assignment -name QIP_FILE ../../megacells/fifo_1kx16_dc_la.qip
+set_global_assignment -name QIP_FILE ../../megacells/fifo_128x64_dc_la.qip
\ No newline at end of file
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- [Commit-gnuradio] r9516 - in gnuradio/branches/developers/ets/inband/usrp/fpga: inband_lib inband_lib/tb megacells toplevel/usrp_inband_usb,
ets <=