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[Commit-gnuradio] r9547 - in gnuradio/branches/developers/ets/inband/usr
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From: |
ets |
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Subject: |
[Commit-gnuradio] r9547 - in gnuradio/branches/developers/ets/inband/usrp/fpga: inband_lib inband_lib/tb megacells |
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Date: |
Tue, 9 Sep 2008 09:27:58 -0600 (MDT) |
Author: ets
Date: 2008-09-09 09:27:56 -0600 (Tue, 09 Sep 2008)
New Revision: 9547
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/dcfifo_generic.v
Removed:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.bsf
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.cmp
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.inc
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.qip
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.v
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la_bb.v
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la_inst.v
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.bsf
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.cmp
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.inc
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.qip
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.v
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la_bb.v
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la_inst.v
Modified:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/packet_builder.v
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_channel_buffer.v
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.qsf
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.v
Log:
generic fifo module, inverted usbclk, overrun clear logic, misc edits
bit->logical ops
Modified:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/packet_builder.v
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/packet_builder.v
2008-09-09 15:20:30 UTC (rev 9546)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/packet_builder.v
2008-09-09 15:27:56 UTC (rev 9547)
@@ -25,7 +25,7 @@
module packet_builder (
// Control / Status
- input clk, //negedge
+ input clk,
input rden, //read enable, resets state when clear
// Header inputs
@@ -95,7 +95,7 @@
end
//Timing logic
- always @(negedge clk) begin
+ always @(posedge clk) begin
if (!rden) begin
read_count <= `RD_HEADER1;
packet_complete <= 1'd0;
@@ -130,7 +130,7 @@
end // always
//ack the header fifo when we are done w/ it
- always @(negedge clk) begin
+ always @(posedge clk) begin
if (read_count == `RD_TIMESTAMP2) header_rd <= 1'd1;
else header_rd <= 1'd0;
end
Modified:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2008-09-09 15:20:30 UTC (rev 9546)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2008-09-09 15:27:56 UTC (rev 9547)
@@ -69,7 +69,7 @@
input RD,
output [15:0] usbdata,
output have_pkt_rdy,
- output rx_overrun,
+ output reg rx_overrun,
//Serial / Command Bus //Unused?
input serial_strobe,
@@ -112,6 +112,9 @@
parameter NUM_CHAN = 1;
genvar i;
+
+ wire usbclk_inv;
+ assign usbclk_inv = ~usbclk; //invert so all logic is posedge
/////////////////////////////////////////////////////////////////////////
// Debug assignments
@@ -154,7 +157,7 @@
always @ (posedge rxclk)
iq = rx_wren ? ~iq : 1'b0;
- assign rx_wren = ~reset & ( rxstrobe | iq);
+ assign rx_wren = !reset && ( rxstrobe || iq); //TODO: glitches?
// select the data inputs for each channel
wire [15:0] i_chan_data[4:0];
@@ -194,9 +197,17 @@
wire [0:NUM_CHAN] chans_ready;
assign have_pkt_rdy = chans_ready ? 1'd1 : 1'd0;
- //overrun signals
+
/////////////////////////////////////////////////////////////////////////
+ //overrun signal
wire [NUM_CHAN:0] overrun;
- assign rx_overrun = overrun == 0 ? 1'b0 : 1'b1;
+
+ always @ (posedge usbclk_inv) begin
+ if (reset) rx_overrun <= 1'b0;
+ else begin
+ if (overrun) rx_overrun <= 1'b1;
+ else if (clear_status) rx_overrun <= 1'b0;
+ end
+ end
/////////////////////////////////////////////////////////////////////////
// Process command data from tx / cmd_reader
@@ -257,8 +268,9 @@
assign i_header_data[i][`CB_NON_INPUTS] = 0;
//control signals from mux
- assign header_rd[i] = chan_sel == i ? mux_header_rd : 1'd0;
- assign data_rd[i] = chan_sel == i ? mux_chan_rd : 1'd0;
+ //disable when not reading
+ assign header_rd[i] = RD && (chan_sel == i) ? mux_header_rd :
1'd0;
+ assign data_rd[i] = RD && (chan_sel == i) ? mux_chan_rd : 1'd0;
rx_channel_buffer chan_buf[i] (
.reset (reset),
@@ -267,7 +279,7 @@
.wren (i_wren[i]),
.flush_packet (i_flush[i]),
- .rdclk (usbclk),
+ .rdclk (usbclk_inv),
.rd_data_en (data_rd[i]),
.rd_header_en (header_rd[i]),
.num_packets (num_pkt[i]),
@@ -309,12 +321,12 @@
wire switch_ok;
assign switch_ok = !RD || pkt_complete;
- // Handle channel mux selection on usbclk.
+ // Handle channel mux selection on usbclk_inv.
// Only change when when no packet is being sent.
// Use next_chan logic to select the next available
// channel from the last channel we sent.
reg [4:0] last_chan;
- always @ (negedge usbclk)
+ always @ (posedge usbclk_inv)
begin
if (reset) last_chan <= 5'd0;
else begin
@@ -327,7 +339,7 @@
// Packet Builder
packet_builder pb (
// Control / Status
- .clk (usbclk),
+ .clk (usbclk_inv),
.rden (RD),
.header_rd (mux_header_rd),
Modified:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_channel_buffer.v
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_channel_buffer.v
2008-09-09 15:20:30 UTC (rev 9546)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_channel_buffer.v
2008-09-09 15:27:56 UTC (rev 9547)
@@ -53,14 +53,13 @@
,output [9:0] dbg_cd_wrusedw
,output dbg_ph_full,dbg_cd_full,dbg_save_header
);
+
+ parameter CD_FIFO_SIZE = 1024; //Depth of channel data fifo
+ parameter CD_FIFO_SZ_LOG2 = 10;
parameter SAMP_PER_PKT = 252; //16 bit samples
- parameter CD_FIFO_SIZE = 1024; //Depth of channel data fifo
- //don't know if this is possible, it would be nice
- //parameter CD_FIFO_NAME = "fifo_1kx16"; //channel data fifo
implementation name
-
//debug
assign dbg_save_header = save_header;
assign dbg_ph_full = ph_full;
@@ -74,14 +73,20 @@
// Packet header fifo related
wire ph_full;
- fifo_128x64_dc_la ph_fifo (
+ dcfifo_generic #(
+ .WIDTH (64),
+ .NUM_WORDS (128),
+ .ADDR_WIDTH (7), //log2(NUM_WORDS)
+ .SHOW_AHEAD ("ON")
+ )
+ ph_fifo (
.aclr (reset),
// .data (ph_fifo_input),
.data (temp_header),
.wrclk (wrclk),
.wrreq (save_header),
.wrfull (ph_full),
- .rdclk (~rdclk), //negedge
+ .rdclk (rdclk),
.rdreq (rd_header_en),
.rdusedw(num_packets),
.q (o_header_data)
@@ -95,15 +100,20 @@
wire [9:0] cd_wrusedw;
wire cd_full;
- fifo_1kx16_dc_la cd_fifo (
+ dcfifo_generic #(
+ .WIDTH (16),
+ .NUM_WORDS (CD_FIFO_SIZE),
+ .ADDR_WIDTH (CD_FIFO_SZ_LOG2), //log2(NUM_WORDS)
+ .SHOW_AHEAD ("ON")
+ )
+ cd_fifo (
.aclr ( reset ),
.data ( i_chan_data ),
-// .data ( temp_data ),
.wrclk (wrclk),
- .wrreq (wren & ~overrun), //block on overrun
+ .wrreq (wren && !overrun), //block on overrun
.wrfull (cd_full),
.wrusedw (cd_wrusedw),
- .rdclk (~rdclk), //negedge
+ .rdclk (rdclk),
.rdreq (rd_data_en),
.q (o_chan_data)
//debug
@@ -135,13 +145,14 @@
end
else begin
//Overrun logic
- if (ph_full | cd_full) begin
- if (~overrun & ~ph_full) //only flush
header once
+ if (ph_full || cd_full) begin
+ //only flush header once
+ if (!overrun && !ph_full)
do_flush = 1'b1;
overrun = 1'b1;
end
- else if (overrun & ~ph_full & (cd_wrusedw <
(CD_FIFO_SIZE - SAMP_PER_PKT)))
+ else if (overrun && !ph_full && (cd_wrusedw <
(CD_FIFO_SIZE - SAMP_PER_PKT)))
overrun = 1'b0;
if (flush_packet)
Modified:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.qsf
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.qsf
2008-09-09 15:20:30 UTC (rev 9546)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.qsf
2008-09-09 15:27:56 UTC (rev 9547)
@@ -24,23 +24,23 @@
set_global_assignment -name FAMILY Cyclone
-set_global_assignment -name DEVICE EP1C20F400C6
+set_global_assignment -name DEVICE EP1C20F324C8
set_global_assignment -name TOP_LEVEL_ENTITY rx_buffer_inband_tb
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "8.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:29:11 SEPTEMBER
06, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION "8.0 SP1"
-set_global_assignment -name VERILOG_FILE ../inband_packet_defs.v
-set_global_assignment -name VERILOG_FILE ../../megacells/fifo_128x64_dc_la.v
-set_global_assignment -name VERILOG_FILE ../../megacells/fifo_1kx16_dc_la.v
-set_global_assignment -name VERILOG_FILE ../packet_builder.v
-set_global_assignment -name VERILOG_FILE ../rx_buffer_inband.v
-set_global_assignment -name VERILOG_FILE ../rx_channel_buffer.v
-set_global_assignment -name VERILOG_FILE rx_buffer_inband_tb.v
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to |
-section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-set_global_assignment -name SIMULATION_MODE FUNCTIONAL
-set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE
rx_buffer_inband_tb.vwf
\ No newline at end of file
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name FMAX_REQUIREMENT "64 MHz"
+set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE
rx_buffer_inband_tb.vwf
+set_global_assignment -name VERILOG_FILE ../inband_packet_defs.v
+set_global_assignment -name VERILOG_FILE ../../megacells/dcfifo_generic.v
+set_global_assignment -name VERILOG_FILE ../packet_builder.v
+set_global_assignment -name VERILOG_FILE ../rx_buffer_inband.v
+set_global_assignment -name VERILOG_FILE ../rx_channel_buffer.v
+set_global_assignment -name VERILOG_FILE rx_buffer_inband_tb.v
\ No newline at end of file
Modified:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.v
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.v
2008-09-09 15:20:30 UTC (rev 9546)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.v
2008-09-09 15:27:56 UTC (rev 9547)
@@ -105,10 +105,10 @@
.usbdata(usb_data),
.have_pkt_rdy(usb_pkt_rdy),
.rx_overrun(rx_overrun),
+ .clear_status(1'b1),
//Serial / Command Bus
.serial_strobe(serial_strobe),
- .clear_status(clear_status),
.serial_addr(serial_addr),
.serial_data(serial_data),
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/dcfifo_generic.v
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/dcfifo_generic.v
(rev 0)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/dcfifo_generic.v
2008-09-09 15:27:56 UTC (rev 9547)
@@ -0,0 +1,58 @@
+// Generic FIFO module
+// Based on Altera megafunction dcfifo
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module dcfifo_generic
+#(
+ parameter WIDTH = 16,
+ parameter NUM_WORDS = 1024,
+ parameter ADDR_WIDTH = 10, //log2(NUM_WORDS)
+ parameter SHOW_AHEAD = "OFF"
+)
+(
+ input aclr,
+ input [WIDTH-1:0] data,
+ input rdclk,
+ input rdreq,
+ input wrclk,
+ input wrreq,
+ output [WIDTH-1:0] q,
+ output rdempty,
+ output rdfull,
+ output [ADDR_WIDTH-1:0] rdusedw,
+ output wrempty,
+ output wrfull,
+ output [ADDR_WIDTH-1:0] wrusedw
+);
+
+ dcfifo dcfifo_component (
+ .wrclk (wrclk),
+ .rdreq (rdreq),
+ .aclr (aclr),
+ .rdclk (rdclk),
+ .wrreq (wrreq),
+ .data (data),
+ .rdfull (rdfull),
+ .rdempty (rdempty),
+ .wrusedw (wrusedw),
+ .wrfull (wrfull),
+ .wrempty (wrempty),
+ .q (q),
+ .rdusedw (rdusedw));
+ defparam
+ dcfifo_component.add_ram_output_register = "OFF",
+ dcfifo_component.clocks_are_synchronized = "FALSE",
+ dcfifo_component.intended_device_family = "Cyclone",
+ dcfifo_component.lpm_numwords = NUM_WORDS,
+ dcfifo_component.lpm_showahead = SHOW_AHEAD,
+ dcfifo_component.lpm_type = "dcfifo",
+ dcfifo_component.lpm_width = WIDTH,
+ dcfifo_component.lpm_widthu = ADDR_WIDTH,
+ dcfifo_component.overflow_checking = "ON",
+ dcfifo_component.underflow_checking = "ON",
+ dcfifo_component.use_eab = "ON";
+
+
+endmodule
Deleted:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.bsf
Deleted:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.cmp
Deleted:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.inc
Deleted:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.qip
Deleted:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la.v
Deleted:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la_bb.v
Deleted:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_128x64_dc_la_inst.v
Deleted:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.bsf
Deleted:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.cmp
Deleted:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.inc
Deleted:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.qip
Deleted:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la.v
Deleted:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la_bb.v
Deleted:
gnuradio/branches/developers/ets/inband/usrp/fpga/megacells/fifo_1kx16_dc_la_inst.v
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